Transcript PPT - Solarlits

Overview of CMOS Photonics
Technology
Irfan Ullah
Department of Information and Communication Engineering
Myongji university, Yongin, South Korea
Copyright © solarlits.com
Outline
• Introduction
• Blue waters
• Core-to-Core communication
• CMOS photonics structure
• Core-to-Core CMOS photonics
• Research by Intel
• Research by IBM
• Conclusion
Introduction
•
•
OCP (Open Core Protocol)
Interconnects IP cores to on-chip bus
Introduction Cont’d..
•
SOC Bus architecture
Introduction Cont’d..
Introduction Cont’d..
Intel shows off 80-core processor
•The chip also contains 80 routers
•80 cores in 10 rows
•62 watts
IEEE International Solid State Circuits Conference 2007
Introduction Cont’d..
Clear speed CXS700 processor
•96 processing elements
•Package size 40mm×40mm
•96GFLOPS
•Power consumption is Less than 9 Watt
Core-to-Core communication
Scalability
• Must accelerate single apps, not just run more apps in parallel
• Efficient core-to-core communication is crucial
Programming
• Traditional parallel programming techniques are hard
• Multicores are ubiquitous and must be programmable by anyone
Power
• More cores and more communication  more power
Core-to-Core communication Cont’d..
• Single shared resource
• Uniform communication cost
• Communication through memory
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• Doesn’t scale to many cores due
to contention and long wires
• Scalable up to about 8 cores
BUS
L2 Cache
DRAM
Point-to-Point Mesh Network
• More energy efficient than bus
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DRAM
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DRAM
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DRAM
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DRAM
• Scalable to hundreds of cores
Point-to-Point Mesh Network Cont’d..
Programming
• Small cores solve the physical scaling challenge, but programming
remains a barrier
• Parallelizing applications to thousands of cores is hard
• For high performance, communication and locality must be
managed
Observations
• A cheap broadcast communication mechanism can make
programming easier
• On-chip optical components enable cheap, energy-efficient
broadcast
CMOS photonics structure
•
•
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Fiber optics has a lot to offer in the speed of data transmission
CMOS (Complementary metal–oxide–semiconductor) manufacturing
processes have a lot to offer in making things smaller, cheaper, and
faster
It would only make sense that putting these two things
together
Core-to-Core CMOS photonics
• 64 cores
• Signal passes through every core
• Signal reaches all cores in <2ns
optical waveguide
MIT COMPUTER SCIENCE AND ARTIFICIAL INTELLIGENCE LAB
Core-to-Core CMOS photonics Cont’d..
N
cores
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MIT COMPUTER SCIENCE AND ARTIFICIAL INTELLIGENCE LAB
Core-to-Core CMOS photonics Cont’d..
 Each core sends data using a different wavelength  no contention
 Data is sent once, any or all cores can receive it  efficient broadcast
multi-wavelength source waveguide
modulator
data waveguide
modulator
driver
filter
transimpedance
amplifier
photodetector
flip-flop
sending core
flip-flop
receiving core
15
MIT COMPUTER SCIENCE AND ARTIFICIAL INTELLIGENCE LAB
Results
Electrical
Optical
64-core system (65nm process)
64-core system (65nm process)
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Peak performance: 64 GOPS
Chip power: 24 W
Theoretical power eff.: 2.7 GOPS/W
Effective performance: 7.3 GOPS

Giga Operations Per Second
 Effective power eff.: 0.3 GOPS/W
 Total system power: 150 W
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Peak performance: 64 GOPS
Chip power: 25.5 W
Theoretical power eff.: 2.5 GOPS/W
Effective performance: 38.0 GOPS
Effective power eff.: 1.5 GOPS/W
Total system power: 153 W
Optical communications require a small amount of
additional system power but allow for much better
utilization of computational resources.
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Optical network for 64-core (Butter-fat-tree)
Optical network for 64-core (Floor plan)
6×6 router architecture
Optical interconnection structure
Towards reconfigurable optical networks on chip, ReCoSoC'05
Optical Bus structure using TDM and WDM
Towards reconfigurable optical networks on chip, ReCoSoC'05
Optoelectronic conversion
Towards reconfigurable optical networks on chip, ReCoSoC'05
Optical Network-on-Chip
 4×4 optical network
Heterogeneous modelling of an Optical Network-on-Chip with SystemC, IEEE, 2005
Optical Network-on-Chip Cont’d..
 SystemC model
Heterogeneous modelling of an Optical Network-on-Chip with SystemC, IEEE, 2005
Research by INTEL
• 50Gbps Silicon Photonics link
Research by INTEL Cont’d..
Research by INTEL Cont’d..
Research by INTEL Cont’d..
Research by INTEL Cont’d..
Research by IBM
Research by IBM Cont’d..
Research by IBM Cont’d..
Research by IBM Cont’d..
Links
Length
BW
Power
~100 k
~1 cm
~1 Tbps
<10mW
Conclusion
Conclusion Cont’d..
Loss
CMOS photonics <0.1dB/cm, optical communication < 2dB/km
More number of channels through single waveguide with high
data rate
For Core-to-Core
• Easy point to point communication
• Very efficient
For SOC
• Point to point communication is not very efficient
• Every segment require different communication speed
• High speed segments can be communicated through optical
communication
• Also, different segments through single Bus (Optical
waveguide).
Thanks
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