Transcript Lecture 3: Thin films

Thin films
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How thin ?
27 Å = 2.7 nm
Thin film solar cell
0.5 µm
50 nm
2 µm
1 µm
Poortmans: Thin film solar cells
Thin films: different from bulk?
• Properties thickness dependent
electrical (resistivity)
optical (transmission)
mechanical (Young’s modulus)
thermal (conductivity)
• Structure: amorphous, polycrystalline or single crystalline
• Structure depends on deposition method
• Structure changes in high temperature steps
• Often severe stresses (tensile or compressive)
Thickness dependent resistivity
Thickness dependent structure and
dielectric constant
Atomic Layer Deposited SrTiO3
Vehkamäki
Thickness dependent structure (2)
High resolution TEM pictures
ALD deposited ZrO2: the 4
nm thick film Is amorphous.
ALD deposited ZrO2: 12 nm thick film
is polycrystalline.
from ref. Kukli 2007.
PVD: Physical Vapor Deposition
The whole wafer is
covered by the
deposited film.
Evaporation
Simple:
wafer
Heat metal until vapor pressure high
enough  metal vapor will be
transported in vacuum to the wafer.
Metal vapor condensation results in
film growth.
electron
beam gun
crucible
Very few parameters to change 
Cannot optimize film quality.
Sputtering
target
Electric field excites argon
plasma.
Accelerated argon ions hit metal
atoms from target.
Target atoms are transported in
vacuum to the wafer.
wafer
Many parameters:
power, pressure, temperature,
gas specie (Ar usually)
Videos
Sputtering animation: https://www.youtube.com/watch?v=8mVK5dwyoEY
Metallic films usually by PVD
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conductors (Al, Au, Cu)
resistors (Ta, W, Pt)
capacitor electrodes (poly-Si, Al, Mo)
mechanical materials (Al-movable mirrors)
magnetic materials (Ni coils)
protective coatings (Cr, Ni etch masks)
optical materials (mirrors, reflectors, IR filters)
catalysts (Pt, Pd in chemical sensors)
CVD: Chemical Vapor Deposition
gas phase convection
diffusion through
boundary layer
surface processes
(adsorption, film
deposition, desorption)
The whole wafer is covered by the deposited film.
Common CVD processes
• Gases in  solid product + gas products
• SiH4 (g)  Si (s) + 2 H2 (g)
• SiCl4 (g) + 2 H2 (g) + O2 (g) 
SiO2 (s) + 4 HCl (g)
• 3 SiH2Cl2 (g) + 4 NH3 (g) 
Si3N4 (s) + 6 H2 (g) + 6 HCl (g)
• WF6 (g) + 3 H2 (g)  W (s) + 6 HF (g)
Thermal oxidation vs. CVD oxide
Si + O2  SiO2
thermal,
1000oC
oxide
silicon
silicon
SiH4 + N2O  SiO2 + 2H2 + N2
aluminum
oxide
aluminum
silicon
silicon
(PE)CVD
300-450oC
Applicable
only on
silicon.
High
temperature.
Deposition
also on
metals.
Low
temperature.
poly = CVD polysilicon
=polycrystalline silicon
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SiH4 (g) ==> Si (s) + 2 H2 (g)
Deposited by CVD at 625oC
Usually deposited undoped
Doping after deposition by diffusion/implantation
Annealing typically 950oC, 1 h to active dopants
Heavy doping ca. 500 µΩ-cm
Grain size ca. 200-300 nm
Annealing changes film stress (and grain size)
Typical thickness 100 nm-2 µm
Plasma Enhanced CVD
Deposition can be
done at 300oC.
Thermal CVD is
usually 400-700oC
(Thermal oxidation at
1000oC)
Oxide:
SiH4 (g) + N2O (g) ==> SiO2 (s) + N2 (g) + 2H2 (g)
Nitride:
3 SiH2Cl2 (g) + 4 NH3 (g) ==> Si3N4 (s) + 6 H2 (g) + 6 HCl (g)
SiNx:H: thermal vs. plasma
Thermal CVD at 900oC
PECVD at 300oC
Smith: J.Electrochem.Soc. 137 (1990), p. 614
Dielectric films
SiO2
SiO2
SiO2
SiO2
gate oxide in CMOS
isolation oxide in CMOS
diffusion mask
etch mask in MEMS
1-50 nm
100-1000 nm
500 nm
100-1000 nm
Si3N4 oxidation mask
Si3N4 membrane in MEMS
100 nm
50-200 nm
Si3N4 capacitor dielectric
Al2O3 capacitor dielectric
HfO2 capacitor dielectric
5-20 nm
1-20 nm
1-20 nm
SiNx
500-1000 nm
passivation coating
Sample wafers !
ALD: Atomic Layer Deposition
Precursors introduced in pulses, with purging in-between
Tetramethyl aluminum and water  Al2O3 (+ CH4 as gaseous byproduct)
Pulse-by-pulse mass increase
ALD Al2O3
Temperature 200oC (from 50-300oC)
1st precursor: Al(CH3)3, pulse time 1 sec
Purge with nitrogen, pulse 1 sec
2nd precursor: H2O, 1 sec
Purge with nitrogen, 5 secs
 8 secs/cycle  450 cycles/hour
1.1Å/cycle (=0.11 nm/cycle)  ca. 50 nm/hour
Total reaction:
2 Al(CH3)3 + 3 H2O  Al2O3 (s) + 6 CH4 (g)
Videos
ALD: https://www.youtube.com/watch?v=HUsOMnV65jk
ALD films
• Al2O3
• Al2O3
• HfO2
diffusion barrier
hard mask in etching
capacitor dielectric
1-20 nm
1-20 nm
1-20 nm
• TiN
• TiN
• TaN
electrode
protective coating
barrier layer
50-100 nm
50-100 nm
1-10 nm
• Pt
catalyst
1-5 nm
Step coverage in deposition
H
A
B
Ratio of film thickness
on sidewall to horizontal
surfaces (100% =
conformal coverage)
Cote, D.R. et al: Low-temperature CVD processes and dielectrics, IBM
J.Res.Dev. 39 (1995), p. 437
ALD step coverage
Excellent conformality: deposition is a surface controlled
reaction.
Al2O3/TiO2 nanolaminate
TiN barrier
Franssila: Microfabrication
Thin film patterns
Thin film deposition covers the whole wafer.
If you want patterns of films, you have to do lithography
and etching.
Lithography
Etching
Remove photoresist
Two patterns
Two aligned layers
<Si>
If two layers are
perfectly aligned,
they were made in
the same litho &
etch steps.
<Si>
Otherwise alignment
error would be visible.
Alignment error
rule of thumb: 1/3 of
minimum linewidth.
Electroplating
Typical plated metals:
-nickel (Ni)
-copper (Cu)
-gold (Au)
Not applicable to:
-aluminum (Al)
-most refractory metals
(W, Ti, ...)
Groove filling by plating
Seed layer
deposition
Copper
electroplating
Polishing
excess copper
away
Electroplating into resist structure
a) Seed layer sputtering and lithography
b) Electroplating metal
c) Resist stripping
d) Seed layer removal
Why use electroplating ?
Metals like copper and gold do
not have anisotropic plasma
etch processes available
 If you want vertical walls,
electroplating is a solution.
Electroplating pros and cons
Simple method: Edison used it in 1800’s
Cost effective: metals stay usable in solution
(cf. sputtering: they are all over the chamber)
Compatible with resists
Only method to make really thick metals (>5 µm)
Applicable to only a few metals: Au, Ni, Cu
These metals cannot be plasma etched  must use
if you want thick patterned metals.
Stresses in thin films
The substrate is in opposite stress state !
Origin of stress
• Extrinsic stresses:
thermal expansion mismatch
Intrinsic stresses: deposition process dependent
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low energy deposition
 no energy for relaxation process
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high energy deposition
 non-equilibrium, forced positions
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impurities, voids, grain boundaries
Cantilever bending
Fang, W. & C.-Y. Lo, On the thermal expansion coefficients of thin films, Sensors &Actuators 84 (2000), p. 310
Stresses in bimetal cantilever
Acoustic multilayers
Glass wafer
Al
Mo
(300 nm)
(50 nm)
ZnO
(2300 nm)
Au
(200 nm)
Ni
(50 nm)
SiO2
W
TiW
SiO2
W
TiW
(1580 nm)
(1350 nm)
(30 nm)
(1580 nm)
(1350 nm)
(30 nm)
Thin films
• On this course, we are interested in
applications of thin films in microfabrication
• Prof. Jari Koskinen is teaching Thin film
technology (period IV):
• “Principles of vacuum technology, surface physics
and surface-ion interactions and low pressure plasma.
Thin film methods: Physical vapor deposition,
chemical vapor deposition, and other plasma.
Characterization methods for thin films to determine,
structure, composition, and mechanical and optical
properties.”