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Microfabrication
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Q1: JFET fabrication process
Explain step-by-step the fabrication process of the JFET shown
below. Make a numbered list with one major process on each
line (major processes F, L, E, S, O, D, I, X)
Estimate epi thickness, junction depths and film thicknesses.
If minimum linewidth and space available are 2 µm and the
source is a square and teh gate is an U-shape around it, draw
top view and calculate the size of the transistor.
gate
source
n- epi
n+
p+
n+ substrate
drain
gate
p+
Hint: the ”black”
metal on drain,
gate and source is
aluminum.
Q2: Passives
What is the nitride thickness if areal capacitance density is 4 nF/mm2, and
nitride =7 ?
Why is the capacitor bottom contact hole made by plasma etching and top
contact hole by wet etching ?
SiCr thin film resistor resistivity is 2000 µOhm-cm. Design a 5 kOhm
resistor using 3 µm LW !
SiCr resistor
Q3: Diffusion
What is the diffusion time required to form a pnjunction at 1 µm depth in 1000C when boron
predeposition is 1014 cm-2 and phosphorous doped
wafer (1015 cm-3) is used.
Hint: Equation 14.8 cannot be solved in closed form.
Try different times, and iterate to find solutions on
both sides of 1 µm junction depth.

Q0

x j  4 Dt  ln 
 C subs Dt




Q4: Step coverage
Draw step coverage
of 200 nm thick
thin film deposition
with the following
processes:
a) ALD
b) Sputtering
c) Evaporation
d) Thermal CVD
e) PECVD.
The figure is drawn
to scale: both films
are 500 nm thick
and trench width is
800 nm.
Copy this 5 times: only one process per figure.
Q5: Implantation
Draw projected range as dotted line for the cases shown below. Use
figures from Chapter 15 as your guide in estimating depths.
100
nm
oxide
100 nm
Arsenic at 50 keV
20 nm
oxide
100 nm
Boron 150 keV
Poly
200
nm
100 nm
Phosphorous 150 keV
Q6: Polishing vs. etching
Explore etching vs. polishing:
•
•
•
•
•
•
What are the similarities ?
What are the differences ?
Materialswise ?
Equipmentwise ?
Applicationwise ?
Ratewise ? Selectivitywise ?