Transcript DIFs - LAL

The DHCAL DIF Board
For the M2 Prototype
Julie Prast, LAPP, Annecy
Julie Prast, Calice Electronics
Meeting at London, January 2008
Architecture of the DIF board
DIF
Power
Supplies
+/- 6V
Monitoring
LDO
+/-5V
3.3V
2.5V
…..
JTAG
USB
S
L
A
B
FPGA
ASIC Config
ASIC read
DAQ interface
Slow control
LDA
(HDMI)
EP3C16F484
DAQ0
(SCSI)
ADC
HARDROCs analog output
DIF
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The DHCAL DIF Board for the m2 Prototype
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The Analog Part
Addr
USB
EP3C16F484
DEMUX
FPGA
En_otaq<1..32>
SLAB
ADC
AD9220
DAQ0
HARDROCs analog output
•
An ADC has been added to read the analog output from the FPGA (ie without the
analog DAQ).
•
ADC 12 bits, 10MSPS, already tested by LAL team : AD9220.
•
One ASIC among 32 max, is selected from the FPGA using the en_otaq signal. To
decrease the nb of pins on the FPGA a DEMUX is used.
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The DHCAL DIF Board for the m2 Prototype
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The DHCAL DIF Board
•
•
•
•
Separated from the slab for more flexibility.
Can handle slab what ever the nb of HardRoc on it.
Compatible with the DIF Task Force.
Interfaces with :
–
–
–
–
The final DAQ (LDA, …)
The analog DAQ
Neighboring DIFs.
PC through USB for standalone tests and debugs.
• Handle HardROC power cycling.
• Compatible with the ASIC of IPN Lyon.
• High voltage is not foreseen.
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The DHCAL DIF Board for the m2 Prototype
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Interface with the SLAB
DIF
Intermediate
board
Connector to be
chosen. No
special
constraint.
Samtec FSH/ SFMH ?
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• Use of a small intermediate
board, which is specific to the FE
ASIC and ASU.
• The DIF can be used :
SLAB
Connection with
the slab is the
same as the
one between 2
ASUs.
– Whatever the FE ASIC.
– Whatever the slab (RPC, uM)
– Whatever the slab to slab
connection.
• 1rst ASU is the same as the
others.
0 Ω resistor, …
The DHCAL DIF Board for the m2 Prototype
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Still a lot to do …
• Electrical schemes to be finalized :
– Finalize FPGA pin out.
– Finalize LDA to DIF interface (cable length and type, electrical
terminations, …)
– Finalize connectors choice.
– Finalize analog part : EL2140 ? Analog buffer ?
• And all the CAD and the VHDL code …
• Additional human resources for coming months :
– Sebastien Cap from LAPP for the CAD.
– Guillaume Vouters (engineer student) between March and
August for VHDL, tests, ….
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The DHCAL DIF Board for the m2 Prototype
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Status and Agenda
• Schemes are being done.
• Will be circulated before the end of the month.
=> Inputs are very welcome.
• First prototype is awaited for May.
• Expect performing main tests before summer.
• Chistophe Combaret (Lyon) is in charge of the test
Software.
• DIFs should be available for the m2 test at the
beginning of the fall (end of the summer for Imad).
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VHDL Librairies
• One of the aim of the DIF task force is to create a
repository for the VHDL blocks that can be common for
the different subdetector groups :
• I proposed in a message sent on November 21st to
collect and order them.
• Christophe Combaret will manage the storage server at
IPNL.
• Bart sent a kind of DIF architecture.
• Francois Wicek sent the slow control block for skiroc.
• Now we need more contributions to get richer the
librairie.
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The DHCAL DIF Board for the m2 Prototype
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