Transcript I LOAD 1.5 x 2.0 x 0.75 mm 8 pin

An Introduction to Silego's Ultra Low RDSON Integrated Power Switches
November 2016 v.1.0
Silego Technology Confidential
Silego Integrated Power Switch (IPS) Categories
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Silego Integrated Power Switch Advantages
Proprietary CuFET™ Technology
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Ultra low RDSON
– nFETs: Singles as low as 4 mΩ; Back-to-back (B2B), Reverse-current Block (RCB) as low as 15 mΩ
– pFETs: Single/duals as low as 23 mΩ
•
Ultra-small package sizes: 1 mm2 to 4 mm2 ST[D/Q]FNs, 0.4 mm pitch
•
Continuous operating currents: 1 A to 9 A
Greater flexibility in power sequencing
•
•
Fixed or adjustable VOUT eliminates “RC” tuning variation
Faster overall power-up sequencing
controlled inrush current
Built-in System-level Protection Circuits
•
Input under/over-voltage protection
•
Fixed or resistor-adjustable current limit
•
Short-circuit protection
•
Thermal shutdown with auto restart
•
Reverse-current blocking
Logic-level Turn-on Signaling
•
Eliminates external level shift or charge pump circuitry to drive FET
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Silego’s Integrated CuFET™ MOSFET Technology
• Single-die Integration:
• Cu-FET™ Technology → Inverted-die packaging → Eliminates bond wires & lead frame
• 0.18-µm Control Circuitry + High-IDS/Low RDSON n/p-channel MOSFETs
• Foundry Process: Low-voltage IPSs → 3.6V or 5V CMOS Logic
24V High-voltage IPSs → 5V CMOS Logic + High-voltage Add-on Module
Low sheet ρ interconnects
DRAIN
SOURCE
Octagonal FET “Cell”
Control Circuit
Top-side Redistribution Layer
GATE
Metal
Layers
& Vias
GATE
Channel
20mΩ RDSON ~100,000 FET “cells”
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Channel
Optimal Range:
1A ≤ IDS ≤ 10A
Note: Not to scale
Silego’s Integrated CuFET™ MOSFET Technology
(for Flip Chip)
TDFN
Lead Frame
Low sheet ρ Cu pillars
0.55mm
Plastic package
encapsulant
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Note: Not to scale
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Single-channel Integrated Power Switch
MOSFET Circuit
+ Discharge Circuit
An ultra Low RDSON Single-channel Integrated Power Switch,
1.5 x 2.0 mm package
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Typical Block Diagram of Single-channel nFET IPS
Proprietary CuFET™ technology for
very low RDSON
Continuous IDS
Capacitor for adjusting
VOUT slew rate and inrush
current control
Resistor for adjusting
Active Current Limit
threshold
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Downstream Load Details:
a) FPGA or application processor
b) LCD Display
c) BT Radio or WLAN
d) USB or Powered ports
e) Buck/Boost converter or LDO
f) HV fan motor (inductive load)
1.6 x 2.5 x 0.55 mm
16 pin
Typical Block Diagram of Single-channel pFET IPS
Continuous IDS
1.0 x 1.0 x 0.55 mm
4 pin
SLG59M1557V
SLG59M1558V
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Dual-channel nFET Integrated Power Switch
≥4mm2
≥4mm2
MOSFET Channel 1 Circuit
Discharge Channel 1
Discrete Solution:
≥24mm2 + 0402 Rs & Cs
MOSFET Channel 2 Circuit
Discharge Channel 2
Silego Solution: 1.6mm2
incl’g protection ckts
Dual-channel Power Switch
in a 1.0 x 1.6 mm Package
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Typical Block Diagram of Dual-channel nFET IPS
ILOAD1
ILOAD2
1.0 x 3.0 x 0.55 mm
14 pin
SLG59M1527V
SLG59M1603V
SLG59M1612V
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Typical Block Diagram of Dual-channel pFET IPS
1.0 x 1.6 x 0.55 mm
8 pin
SLG59M1638V
SLG59M1639V
SLG59M1640V
SLG59M1641V
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Typical Block Diagram of Single-channel nFET
IPS with Reverse Blocking Feature
ILOAD
1.5 x 2.0 x
0.75 mm 8 pin
SLG59M610V
SLG59M1563V
SLG59M1600V
SLG59M1714V
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GreenFET3 Over-current Protection
If current-limit condition is not triggered,
IPS operates in normal mode. Thermal protection is not activated.
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GreenFET3 Over-current Protection
If current-limit condition is triggered,
then thermal protection is activated.
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GreenFET3 Short-circuit Protection
For short circuit on the VOUT pin – thermal protection is not triggered,
output voltage VOUT = 0V and MOSFET is saved from damage.
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GreenFET3 VOUT Ramp Rate
Conditions: CSLEW = 4 nF; VDD = 5 V; VD = 5 V
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Learn more about GreenFET3 products at our website
http://www.silego.com/products/greenfet3.html

GreenFET3 Product Selector Guide
(English)
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
HFET1 Product Selector Guide

AN-1068 GreenFET3 Integrated
Power Switch Basics