Transcript EE595_Team3_P3_Fall07

Depth Finder 600
EE 595 Capstone Design Project
Fall 2007
Team 3
1
Team #3: Group Members

Adam Davis


Tony Johnson


Peter Meyer


Isaac Krull


Joe Reisinger

Expertise: Digital: PLD/FPGA VHDL
Experience: Associate Applications Engineer @ Rockwell
Expertise: Microprocessors
Experience: Part Time Design Engineer @ Bucyrus
Expertise: Management Skills
Experience: Soldering, Hands-On
Expertise: Calibration, C++ Programming
Experience: Engineering Intern @ Johnson Controls
Expertise: PDP, Reliability
Experience: Systems Engineer @ Baxter Health Care
2
Depth Finder
This product will measure the depth of water.
 This product uses a power supply, receiver, transmitter, microprocessor and user interface.
 This application specific design will relieve the end user of difficult and hard to understand
interfaces while still maintaining reliability for marine applications


This system will use a 12VDC power supply designed for marine use or 8 D Cell batteries.

This is a relatively simple design with 5 separate blocks. It utilizes our strengths as a team
while still delivering key concepts learned in our academic career.
3
Performance Requirements

Functions and Capabilities
Product must be accurate to depths of +/- 5 percent of actual depth @ 60°F
-Depth in Meters must be accurate to depths of +/- 5 percent of actual depth
Product must be able to measure depths from 2 to 50 feet
-Product must be able to measure depths from 1 to 15 meters
Product must read depth continuously
Must be able to sense under the transducer within a 15 degree cone
Must be able to work both with marine batteries and with D cell batteries
Product must be able to differentiate small objects from the bottom of the lake
4
Performance Requirements

Modes of Operation
The Product shall be able to turn on and off

Power Inputs
The battery must be able to last for 5 hours on full operation without recharge
The product must be able to operate on a standard 12 V marine battery
The product must be able to operate on 8 standard D Cell batteries

Electrical Functions
The product must be able to operate within a voltage range of 10-14.8V

Operator I/O Inputs
The On/Off switch must be a momentary off pushbutton switch
The Feet/Meter switch must be a momentary off pushbutton switch
The Feet/meter display must be a 7 segment LED.
The display must be 0.75 in by 1.48 in.
The display must be readable up to 5 feet.

Mechanical Interfaces
The product must be able to mount onto an L bracket
5
Standard Requirements

Environment & Safety
The product shall be able to operate in temperatures between 0 and 55 degrees Celsius
The product shall be able to operate in 0-90% non-condensing humidity
The product shall be able to operate in altitude ranges from sea level to 8000 feet
The product shall be able to be stored in temperature ranging from -6 to 65 degrees Celsius
The product shall be able to be stored in 0-90% non-condensing humidity
The product shall be able to be stored in altitudes ranging from -500 to 60000 feet
The product shall be able to be stored without operation for 10 years
The product must be able to be immersed in water for no more than 5 seconds and still be able to
operate correctly.
In the event of submersion for longer than 5 seconds, the device shall fail in a manor as to not
cause bodily injury.
6
System - Std Reqs: Market & Business Case
Requirement
 Competitors
Market Size
 Average List Price
 Market Geography
 Market Demography
 Intended Application
 Material Cost
 Manufacturing Cost
 Annual Volume

Units to Specify
 Humminbird, Lowrance, Eagle,
Garmin.
 10M
 $150
 USA and Canada
 14- up, Male and Female
 Marine
 $57
 $67
 10000 Units/yr
7
Refined Block Diagram
Key
Power
Analog Signal
Ping Signal
Push Button #1
Push Button #2
LED Display
Ultrasonic
Transmitter
9V
Peter
Backlight for label
Control
Power Source
10 – 14.8 V
Joe
Vcc = 5 V
Vcc = 9 V
Ultrasonic
Receiver
5, 9 V
Isaac
CPLD
5V
Adam
User Interface
5V
Tony
8
Refined Block Diagram Description Table
Block
#
Block
Name
Owner
Brief Description
Of Block Function
Power
Interfaces
Digital
Interfaces
Analog
Interfaces
1
Power Supply
Joe
Reisinger
Converts 10-14.8 VDC to 5VDC
and 9VDC with minimal ripple
In: 1014.8VDC
Out: 5VDC,
9VDC
None
Out: Vbat
2
CPLD
Adam Davis
CPU design using CPLD
Clock determined by required time
delay
In: 5VDC
Out: User
Interface
In: Push
Buttons
In: Input from
Transducer
circuit
3
User Interface
Tony
Johnson
Allows the user to interface with
the device, including display of
depth and push buttons for options
In: 5VDC
In: CPLD
Out: Push
Buttons
None
4
Transmitter
Peter Meyer
Transmits a signal into the water
for reflection detection for the
receiver
In: 9VDC
None
Out: Signal
In: Signal from
CPLD
5
Receiver
Isaac Krull
Receives signals from the water
and sends the corresponding
signals to the CPLD
In: 5VDC,
9VDC
None
Out: Signal to
CPLD
9
Block Signal Table: Power
Power Signals
Power1 (Battery to Power Supply)
Power2(Supply to U/I-(LEDs))
Power3(Supply to Microprocessor)
Power4(Supply to Transformer)
Power5(Supply to Receiver)
Power6(Supply to Receiver)
Power7(Supply to Transmitter)
Type Direction
DC
DC
DC
DC
DC
DC
DC
Input
Input
Input
Input
Input
Input
Input
Block-Block
Voltage Voltage Range
Freq Freq Range % V-Reg V-Ripple
Interconnect Nominal
Min
Max Nominal Min Max
Max
Max
PCB Trace
12
10
14.8
N/A
N/A
N/A
15
1
Connector Cable
5
4.75
5.25
N/A
N/A
N/A
5
0.1
Connector Cable
5
4.75
5.25
N/A
N/A
N/A
5
0.1
PCB Trace
12
10
14.8
N/A
N/A
N/A
15
1
PCB Trace
5
4.75
5.25
N/A
N/A
N/A
5
0.1
PCB Trace
9
8.5
9.5
N/A
N/A
N/A
10
0.2
PCB Trace
9
8.5
9.5
N/A
N/A
N/A
5
0.1
10
Block Signal Table: Digital
Digital Signals
To - From
Block #'s
Type
Dir
Block-Block
Interconnect
Output
Structure
Input
Structure
Tech
Freq
Nominal
Logic
Voltage
Push Button #1
Push Button #2
Ping, Signal from Receiver Block
LED Display
LED Back Lit Display
Crystal
To Block 3
To Block 3
From Block 5
To Block 3
To Block 3
From Block 4
Digital
Digital
Digital
Digital
Power
Clock
Output
Output
Input
Output
Output
Input
PCB/Wire
PCB/Wire
Wire
PCB/Wire
PCB/Wire
PCB
Standard
Standard
N/A
Standard
Standard
N/A
N/A
N/A
Standard
N/A
N/A
Clock
TTL
TTL
Other
Other
Other
Clock
DC
DC
Variable
DC
DC
24.08kHz
5V
5V
5V
5V
5V
Digital Signals
To - From
Block #'s
Type
Dir
Push Button #1
Push Button #2
Ping, Signal from Receiver Block
LED Display
LED Back Lit Display
Clock
To Block 3
To Block 3
From Block 5
To Block 3
To Block 3
From Block 4
Digital
Digital
Digital
Digital
Power
Clock
Output
Output
Input
Output
Output
Input
Digital Signals
To - From
Block #'s
Type
Dir
To Block 3
To Block 3
From Block 5
To Block 3
To Block 3
From Block 4
Digital
Digital
Digital
Digital
Power
Clock
Push Button #1
Push Button #2
Ping, Signal from Receiver Block
LED Display
LED Back Lit Display
Crystal
Vih Min
N/A
N/A
2.1V
N/A
N/A
2.1V
Voh Min
Output
Output
Input
Output
Output
Input
2.4V
2.4V
N/A
9.0V
9.0V
N/A
Input Characteristics
Iih Max
ViL Max IiL Max
N/A
N/A
10uA
N/A
N/A
10uA
N/A
N/A
0.8V
N/A
N/A
0.8V
Output Characteristics
Ioh Max VoL Max
-3.2mA
N/A
N/A
100mA
100mA
N/A
N/A
0.5V
N/A
0.5V
0.5V
N/A
N/A
N/A
-10uA
N/A
N/A
-10uA
Vth Min Vth Max
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
IoL Max
N/A
-1.2mA
N/A
1uA
1uA
N/A
11
Block Signal Table: Analog
To - From
Block #'s
2
2
Type
Direction
Analog
Analog
Output
Input
Block-Block
Interconnect
Ultrasonic Transducer
Ultrasonic Transducer
Coupling
Voltage Max
Amplitude
150 V
5V
Impedance
Min
Max
450
550
450
550
Freq Range
Min
Max
49 kHz 51 kHz
49 kHz 51 kHz
12
Leakage
Max
Ethical/Societal Issues

Our depth finder is at risk of electrical faults and possible electrocution if
proper procedures to eliminate these risks are not taken.
Our unit will need to be enclosed in a waterproof enclosure.
Proper safety grounds must also be implemented.
– These actions will greatly reduce the risk of possible electrical faults or
electrocution.

The engineering of our sonar transmitter and receiver is the most critical
part of our product.
If this isn’t functioning 100% correct, the product will be useless.
To ensure this area of engineering is 100% correct numerous extensive tests
will be performed on the transmitter and receiver components.
13
Applicable Patents
Name: Portable Fish Finder
Patent Number: 6791902
Date: September 14, 2004
 This patent could be designed around if we intended our unit to be permanently used on a boat
and not portable. A different mounting device other than a suction cup could be used to mount
the transducer to the boat.
Name: Method for determining depth values of a body of water
Patent Number: 5465622
Date: November 14, 1995

This patent could be designed around by omitting the velocity sensor used and assume the
velocity of the sound signal to be relatively constant. For averages lakes, the velocity will
not vary greatly with the change in depth. The depth our depth finder is designed for won’t
be affected by changing velocity due to depth.
Name: Depth Finder having variable measurement capabilities
Patent Number: 5065371
Date: November 11, 1991

This patent could be designed around by utilizing a different display than a liquid crystal
display. A typical CRT display or LED display could be used instead. Also, our depth finder
would be designed for use in fresh water only.
14
Burns from Hot, Touchable Surfaces

Mitigation Design/Devices/Materials/Packaging
In the event of failure, the battery and power supply shall be isolated
from the user with some sort of protective cover.

Affected Blocks
Power Supply

Test(s) Required to Verify Protection
Continuous use and thermal testing
15
Unsafe Single Point/Device Failures

Mitigation Design/Devices/Materials/Packaging
In case of device failure, an audible alarm will sound
Materials shall be of non-corrosive, thermal treated material

Affected Blocks
User Interface, Transducer, CPLD

Test(s) Required to Verify Protection
Induce a failure during normal operation
Conduct environmental testing on prototype materials
16
Electric Shock

Mitigation Design/Devices/Materials/Packaging
The user interface will be isolated by using dielectric materials.
Grounding and low potential at all conductive surfaces.
Insulation of high voltages

Affected Blocks
User interface
Power Supply
Transducer Circuit

Test(s) Required to Verify Protection
Electrostatic Discharge Testing to 15kV
Surface voltage potential sensing at all high voltage contained components
17
Abusive Or Unknowing Users

Mitigation Design/Devices/Materials/Packaging
Utilize warning labels on the device and user manual to not allow children to use
the device.
Design a carrying case which is lockable to prevent unwanted use by children.
Allow the operation of push buttons at required time intervals throughout the use
of the CPLD/software

Affected Blocks
CPLD

Test(s) Required to Verify Protection
Random button pushing
18
Sharp Edges & Pinch Points

Mitigation Design/Devices/Materials/Packaging
All corners and edges will be rounded. Warning indications will be
documented in the user manual and near any trouble spots.
The battery cable will consist of pinch proof connectors. Also, the user
interface will consist of push buttons rather than switches.

Affected Blocks
User Interface, Power supply

Test(s) Required to Verify Protection
Physical inspection
19
Magnetic Field Energy

Mitigation Design/Devices/Materials/Packaging
Twisted shielded cables

Affected Blocks
Transmitter and Receiver

Test(s) Required to Verify Protection
Magnetic Field Immunity
20
Electro-Static Discharge

Mitigation Design/Devices/Materials/Packaging
Electronic shielded enclosures
Ground coupled user inputs

Affected Blocks
User Interface

Test(s) Required to Verify Protection
ESD Immunity Test
21
RF Electric Field Energy

Mitigation Design/Devices/Materials/Packaging
RF shielded signal cables

Affected Blocks
Transmitter, Receiver, CPLD

Test(s) Required to Verify Protection
RF Conducted Immunity
22
Interference with Other Electronic Systems

Mitigation Design/Devices/Materials/Packaging
Fuse to isolate power supply

Affected Blocks
Power Supply

Test(s) Required to Verify Protection
Power Surge Immunity Test
23
The Depth Finder 600
Task
2007
Week 1
Week 2
Week 3
Week 4
Week 5
Week 6
Week 7
Week 8
Week 9
Week 10 Week 11 Week 12 Week 13 Week 14 Week 15
Planning
5-Sep
25-Sep
Product Design
18-Sep
Process Design/
Development
Product & Process
Validation
Feedback/
Assessment and
Corrective Action
18-Sep
31-Oct
27-Oct
31-Oct
21-Nov
21-Nov
5-Dec
Production
6-Dec
24
Block Prototyping Plan Template
Block
Name
Block Area (cm2)
Board #
Board
Substrate
Type
Comp
Attachment
Type
Board
Dimensions
(cm x cm)
Types of
Connectors
CPLD
2.413x1.5875
1
PCB
Through Hole
9.652x6.35
Trace
U/I
4.826x3.175
1
PCB
Through Hole
9.652x6.35
Trace
Power Supply 3.413x1.5875
1
PCB
Through Hole
9.652x6.35
Trace/Pad
Receiver
4.826x3.175
2
PCB
Through Hole
9.652x6.35
Trace
Transmitter
4.826x3.715
2
PCB
Through Hole
9.652x6.35
Trace
25
Block Description and Purpose Slide
Power Supply
•The power supply will consist of a battery pack containing 8 D-cell
batteries. Also, it will be capable of connecting to a 12V marine
battery.
-It will contain a 5V regulator needed by the CPLD, Display, and
Receiver blocks
-It will contain a 9V regulator needed by the Transmitter and
Receiver block
-A transformer will drive the transducer
-A transistor, supplied by 12V, will act as a “switch” for the
transformer.
•The purpose of this block is to supply all blocks with the voltage
necessary to perform their functions.
-Powers the transducer and helps to provide a means of
portability.
-A 4 amp max current will be supplied.
-The On/Off switch for power will be located on the display.
26
Standard Requirements
Max Operating Temp Range:
Operating Voltage Range:
Power Source:
Max Product Volume:
Max Mass:
0C to 55C
10.0V to 14.8V
D-Cell Batteries
500 cm^3
2.5 kg
Performance Requirements
Power Modes:
Min Current Requirements:
Maximum Current Supply:
Transducer Supply Voltage:
Receiver Supply Voltage:
On (+12V), Off
5V: 410 mA
9V: 160 mA
12V: 2 A
4A
150 Vpp @ 50 kHz
5V
27
Block Signal Input/Output Summary
Power Supply
Block Name: Power Block
Block Number: 1
Power Signals
Power1a VCC+5
Power1b VCC+5
Power2 VCC+9
Power3 VCC+12
Analog Signals
XfmrOut
XfmrIn
To - From
Block #'s
To 2,3,
To 5
To 4,5
To 1
To - From
Block #'s
To 5
From 4
Type
DC Power
DC Power
DC Power
DC Power
Type
Analog
Analog
Direction
Output
Output
Output
Output
Direction
Output
Input
Block-Block
Interconnect
PCB Trace
Connector Cable
Connector Cable
PCB Trace
Voltage
Nominal
5.0V
5.0V
9.0V
12V
Block-Block
Interconnect
PCB Trace
PCB Trace
Coupling
Xfmr
Xfmr
Voltage Range
Min
Max
4.75V
5.25V
4.75V
5.25V
8.75V
9.25V
10V
14.8V
Voltage Max
Amplitude
5V
9V
Min
Current
400mA
10mA
160mA
2A
Impedance
Min
Max
Freq
Freq Range
Nominal Min
Max
DC
N/A
DC
N/A
DC
N/A
DC
N/A
Freq Range Leakage
Min
Max
Max
49kHz
51kHz
49kHz
51kHz
28
Block Diagram Breakdown
Power Supply
Transmitter Input
Transistor to
Power transducer
Marine Battery
5V Regulator
To User Interface, CPLD,
Transmitter/Receiver
Switch
+12V
To Transmitter/Receiver Circuit
D-Cell Battery Pack
9V Regulator
29
Block Preliminary Schematic
Power Supply
•+12V supply
•+9V, +5V regulated
•AC signal
generated from
transmitter pulses
•Step-up transformer
to drive transducer
•Need to drive 150V
bias @ transducer
after transmitter
pulses to “listen” for
return signal.
30
Block Preliminary Bill of Materials
Power Supply
Part Number
Description
D-Cell Batteries
D-Cell Battery Package
7805-5V Regulator
7809-9V Regulator
2 pin MTA connector
1uF capacitor ceramic
10uF capacitor-ceramic
Transistor
Transformer
4A fuse
1A fuse
Diode
Zener Diode
Quantity
8
1. 000
1. 000
1. 000
2. 000
4. 000
2. 000
1. 000
1. 000
1. 000
1. 000
2. 000
2. 000
31
Block Detailed Design Calculations &
Component Selection




All components are to be thru-hole. This allows for easier prototyping.
Bypass capacitors are added to both sides of each regulator for decoupling.
The voltage regulators are of TO-220 package. They are cheap, heat sinkable (in case too much current), and
easily mountable
5V: 7V*.750A (max) = 5.25W Using a 20W regulator
9V: 3V*.5A (max) =1.5W Using a 5W regulator
Safety Devices: Fuses, especially for the transducer which has a high current draw.
+12 V supply ~2A in operation, +9 V supply ~160mA
–
 4A fuse
+5 V supply <500mA from display, ~10mA from microprocessor, ~250mA to other board
–


1A fuse
Transistor
2A will flow across the transistor during operation.
The transformer will be supplied 5V, leaving 7V VCE
2A*7V=21W
– The transistor is rated up to 75W
Transformer
5V input
– Need 150V out to secondary
32
DFM Calculations
Power Supply
Passive Discrete Components
Component
Nominal
Value or
Max Value
Tolerance
Around
Nominal
Maximum
Working
Voltage
Composition Q Factor or
Dielectric or Frequency
Form
Variation
Capacitor
1uf
10.00%
20 Tantalum
8.00% Radial
Capacitor
10uf
10.00%
20 Tantalum
8.00% Radial
Package
Analysis Type
DC Gain vs.
Semiconductor Semiconductor
Max Offset Component Slewrate Power Pulse Response Noise and/or V or I
Power &
Package &
Voltage
Variations Bandwidth
& Delay
ripple
Regulation Junction Temps Heatsink
Analog Circuit Type
Power Transistor
1us turn off time 1us turn off time
TO-220
Linear Voltage Regulator 250mV
DC
100mV
5V
TO-220
Linear Voltage Regulator 250mV
DC
100mV
9V
TO-220
33
Transmitter
Block Description and Purpose
The purpose of this block is to provide the signal to drive the
transducer
 Takes DC voltage and turns into 50 kHz square wave
 Square wave is transformed into a sine wave. The sine wave is
amplified and then drives transducer

34
Performance Requirements




Transducer must be in a water-tight enclosure
Must receive between 4.5 and 18 Volts from the power supply
Transducer power supply must be able to generate 16 pulses at
50kHz, and shut off until the pulse is received back.
Amplifier must take approximately 6 V at 200mA, and convert it
to the transducer bias voltage of 150V
35
Block Diagram Breakdown Slide
From Power
50 KHz Signal
Generator
From CPLD:
Control for how
Long signal is
generated
Amplification
Circuit
50 kHz Ultrasonic
Transducer
To CPLD
36
Block Preliminary Schematic
37
Theory of Operation
 LM555 timer chip generates a 50 kHz square
wave
 Disable pin allows CPLD to control periods of
signal generation
 Second-order low-pass filter removes harmonics
to create a more sinusoidal signal
 Sine wave drives the base of a transistor to
power the transducer
38
Important Equations
39
Equation Solutions
Ra arbitrarily chosen as 1 kohm
 C = 1 nF
 f = 50 kHz = 1.44/[(Ra + 2Rb)C]
 Rb = 13.9 kohm
 THIGH = (.693)(Ra + Rb)(C) =

 1.03257 * 10-5

TLOW = (.693)(Rb)(C) =
 9.63 * 10-7
40
Preliminary Bill of Materials




National Semi-Conductor LM555 Timer Chip
RS ¼ Watt, 5% Tolerance Resistors
.01uF Capacitor
1 nF Capacitor
41
Part Rationale

LM555:
Ability to create necessary frequency signal
Ability to be shut off from outside source
Stable operation between 4.5 and 18 Volts
Running temperature range (0-70 degrees C)
Small package type: DIP8
Low-Cost : $1.69 individual cost
42
Part Rationale

RS 271-280 Micro-Size Potentiometer
Compact size
Availability
Easily tunable prototype
Low-cost: $1.49
43
Package Type Rationale

RS ¼ Watt, 5% Tolerance Resistors
Power ratings meet needs: Typically can handle between 200
and 250 Volts. They will not see more than 150 V.
44
Block Signal Input/Output Summary
Transmitter
Block Name: Transmitter Block
Block Number: 4
Power Signals
To - From
Block #'s
Power2VCC+9
From 1
Analog Signals To - From
Block #'s
XfmrIn
To 1
Type
Direction
DC Power Input
Type
Direction
AC Power Output
Block-Block
Interconnect
Voltage
Nominal
Connector Cable 9.0V
Block-Block
Interconnect
PCB Trace
Voltage Range
Freq
Freq Range % V-Reg V-Ripple Current
Min
Max Nominal Min Max
Max
Max
Max
8.75V
9.25V DC
N/A
2.5
Coupling Voltage Max Impedance
Amplitude
Min
Max
Freq Range Leakage
Min Max
Max
Xfmr
49kHz 51kHz
9V
0.025V
45
0.25A
Analog Block DFM - Passive Discrete Table
Passive Discrete Specifications
Nominal
Adjustment
Value or
Range,
Max Value
%/Turn
Tolerance
Around
Nominal
Derated
Pow er
Capacity
Maximum
Working
Voltage
Maximum
Constant
Current
Maximum
Surge
Current
Composition Q Factor or
Dielectric or Frequency
Form
Variation
Package
Component
Resistor
Resistor
Resistor
Capacitor
Capacitor

1k
13.9k
318 Max
.01uF
1nF
1%
1%
1%
10%
10%
0.25
0.25
0.25
50
50
X
X
X
Dielectric
Dielectric
X
X
X
Worst-Case: Square Wave Generator
f = 1.44/[(Ra + 2Rb)C],
– Ra=990-1010, Rb=13761-14039, C=9.9e-10 – 1.01e-9
 f = 49.0-51.0 kHz

Worst-Case: Low-Pass Filter
fb = 1/[6.283(R2C2)1/2
– R = 297-303, C = 9.9e-9 – 1.01e-8
 fb = 52.0 - 54.1 kHz
46
Receiver
 Purpose
The receiver block will amplify an input signal from a
transducer. This amplified signal will than be fed into
a tone decoder which will swing low when the
specified signal is detected. This low will then go into
a voltage comparator to give the microprocessor a
clean signal.
47
Receiver Block Standard Requirements
The receiver block must be able to amplify a signal from +/-5 mV
pk to 5 V pk for input into the tone decoder.
The output must produce a 0 V dc level , 0-800mv and 2.5 to 5V
for logic high, for input to the CPLD.
Standard
Temperature range
Max current
Voltage rating
0-55 C
150 mA
4.5 – 5.5 V
48
Receiver Block Performance
Requirements
-The amplifier block will amplify a signal from the transducer to a
.2 – 4.5 V signal for input to the tone decoder
- The logic low from the tone decoder must be less than 2.5 v,
and have a fall time of less than 50ns.
- The logic High must be greater than 2.5 volts and have a rise
time less than 200 ns
49
Receiver Block Performance
Requirements
- The comparator block will be configured to account for a .25 V
hysteresis
- No potentiometers will be used in the circuit all resistor values
will be calculated based on the 50 kHz signal
50
Block Signal Input/Output Summary
Receiver
Block Name: Receiver
Block Number: 5
Power Signals
To - From
Block #'s
Power1b VCC +5
Power2 VCC +9
From 1
From 1
Digital Signals
To - From
Block #'s
Digital 7 Echo Output
To 2
Analog Signals
To - From
Block #'s
XfmrOut
From 1
Type
Direction
DC Power Input
DC Power Input
Type
Digital
Type
Analog
Dir
Input
Direction
Input
Block-Block
Interconnect
PCB Trace
PCB Trace
Block-Block
Interconnect
Wire
Block-Block
Interconnect
Voltage
Nominal
5.0V
9.0V
Output
Structure
N/A
Voltage Range
Freq
Min
Max Nominal
4.75V
8.75V
Input
Structure
Standard
Coupling Voltage Max
Amplitude
Connector-Cable Xfmr
Standard
Freq Range
Min
Max
5.25V DC
9.25V DC
Tech
N/A
N/A
% V-Reg V-Ripple Current
Max
Max
Max
0.05
0.025
0.1V
0.025V
200 mA
0.25A
Freq
Logic
Input Characteristics
Nominal Voltage Vih Min Iih Max ViL Max IiL Max
CMOS DC
Impedance
Min
Max
5V
2V
Freq Range
Min
Max
49kHz
51kHz
10uA
.8V
20mA
Leakage
Max
N/A
51
Receiver Block Diagram
52
Receiver Schematic
53
Receiver Schematic
A buffer will be placed before the amplification block
 The LM 311 will act as the voltage comparator
ensuring a dc logic low
 150 mA fuses will be added on the 5V power and 9V
line to protect the Tone decoder and other ICs

54
Receiver Design Calculations &
Component Selection
PLL Equations
Fo = 1 / (1.1 x (25k) x .001uf)
 BW = 1070 x sqrt (vi / (fo x .02 uf)
 +/- 5 khz
 Other capacitors on diagram are bypass caps
 Resistor values were chosen for desired gain

55
Receiver Considerations
There is a 30 ns fall time and 150 ns rise time
on output of decoder
 Fo will change +\- .1 % for every 1 degree
change in temperature.
 Bandwidth with change .05% for every 1
degree temperature change

56
Receiver Prototype Cost

7 resistors $.10
2 variable resistors $.75
LM741 $.84
LM311 $.55
LM567 $1.27
4 ceramic capacitors $.15
Total parts cost $4.91

**** All parts are through hole






57
Receiver DFM
Component
R1 R2 R8 R9
R3
R4
R5
R6
R7
R10
C1
C2
C3
C4
C5
Componet
LM741
LM311
LM567
Nominal Value
10k
1k
1M
22k
18 k
.33 k
100 k
.02 uf
.01 uf
.02 uf
.001 uf
.01 uf
Max Offset
Voltage
3 mv
4 mv
Tolerance
Derated Power
capacity
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
1/4 W
Max Working
Voltage
5%
250 V
5%
250 V
5%
250 V
5%
250 V
5%
250 V
5%
250 V
5%
250 V
10%
50 V
10%
50 V
10%
50 V
10%
50 V
10%
50 V
DC gain vs
Gain vs F vs
Phase vs f vs
Comp variation Comp variation Comp variation
50
200
200
Max Working
Current
250 mA
250 mA
250 mA
250 mA
250 mA
250 mA
250 mA
Slewrate Power
Bandwidth
0.5V/us
Composition
Dialectric Form
Carbon Film
Carbon Film
Carbon Film
Carbon Film
Carbon Film
Carbon Film
Carbon Film
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Pulse Response
And Delay
300 ns
200 ns
150 ns Rise time
30 ns fall time
Q Factor Package
f Var
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Input
Output
Z
Z
2M
Design
Purpose
Voltage Divders
Feed Back Rs
Feed Back Rs
Filter
Tunes to 50kHz
Voltage drop
Hysteresis Voltage
Coupling
Band Pass
Band Pass
Tunes to 50kHz
Hysteresis Voltage
Noise or Ripple
Upper to Lower
Hysteresis
.25V
20k
58
User Interface / Display
Purpose: Creates an interface with the CPLD to display the depth
being read. The display also has the capability to switch the output
of the CPLD between English and metric.
The display is a 7 segment LED display with a common anode. The
common anode is connected to +5 volts. The cathodes are
connected to the CPLD along with a current limiting resistor for
each individual LED. The CPLD grounds applicable signals to light
up certain LED’s corresponding to the correct depth reading.
59
Standard Requirements
Max Operating Temp Range:
Min Operating Voltage Range:
Maximum Current Draw:
0C to 55C
4.75V to 5.25V
250mA
Performance Requirements
Power Modes:
Display Type:
Display Char Matrix:
Display Size:
Switch Type:
On / Off / Error
7 Segment LED
3 Char./Row, 1 Row
1.9cm x 3.78cm
On / Off Pushbutton
60
Block Signal Input/Output Summary
User Interface
Block Name: User Interface Block
Block Number: 3
Power Signals
To - From
Block #'s
Power1a VCC +5
From 1
Digital Signals
To - From
Block #'s
Digital1 On/Off Push Button
Digital2 English/Metric Push Button
Digital 3 English LED
Digital 4 Metric LED
Digital 5 LED Display (Qty. 22)
To 2
To 2
From 2
From 2
From 2
Digital Signals
To - From
Block #'s
Digital1 On/Off Push Button
Digital2 English/Metric Push Button
Digital 3 English LED
Digital 4 Metric LED
Digital 5 LED Display (Qty. 22)
To 2
To 2
From 2
From 2
From 2
Type
Direction Block-Block Voltage
Interconnect Nominal
DC Power Input
Type
Digital
Digital
Digital
Digital
Digital
Vih Min
2V
2V
N/A
N/A
N/A
Dir
Output
Output
Input
Input
Input
Iih Max
10uA
10uA
N/A
N/A
N/A
PCB Trace
5.0V
Voltage Range
Min
Max
4.75V
Block-Block Output
Input
Interconnect Structure Structure
PCB
PCB
PCB
PCB
PCB
Trace
Trace
Trace
Trace
Trace
N/A
N/A
N/A
N/A
N/A
Input Characteristics
ViL Max
IiL Max
.8V
.8V
N/A
N/A
N/A
20mA
20mA
N/A
N/A
N/A
Standard
Standard
Standard
Standard
Standard
Vth Min
N/A
N/A
N/A
N/A
N/A
5.25V
Tech
Other
Other
CMOS
CMOS
CMOS
Freq
Nominal
Freq Range
Min
Max
DC
N/A
% V-Reg V-Ripple
Max
Max
0.05
Freq
Logic
Nominal Voltage
DC
DC
DC
DC
DC
5V
5V
5V
5V
5V
Output Characteristics
Vth Max Voh Min Ioh Max VoL Max IoL Max
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2.4V
2.4V
2.4V
N/A
N/A
100uA
100uA
100uA
N/A
N/A
.5V
.5V
.5V
N/A
N/A
24mA
24mA
24mA
61
0.1V
Block Diagram of U/I
+ 5V
English/Metric
Pushbutton
On/Off
Pushbutton
CPLD
2 Wire Array
22 Wire Array
English/Metric
Backlight
LED Display
Resistor
Array
22 Wire Array
62
User Interface Schematic




Common Anodes connected to +5v
CPLD grounds cathode to illuminate LED’s
Current limiting resistors
Momentary on pushbuttons
63
User Interface Block – Bill of Materials
(1) - 7 Segment LED Display – LDT-A512RI
(3) - 270 ohm, 250mW 8 Resistor Array – 4116R-1-271LF
(2) – 150 ohm, 125mW resistor, axial
(2) – 2x5mm Rectangular LED – SSL-LX2573GD
(2) – Momentary SPST NO Push button – D6R60 F1 LFS
(1) – 0.1uF Ceramic Capacitor
64
Calculations / Component Selection
Device Package Type:
LED Forward current:
LED Forward voltage:
Source Voltage:
Current Limiting resistor:
28-Dip 7 Segment LED
Typical 10mA
2.2V Typical, 2.6V Max
5V
(VS-VLED)/270Ω (+/-2%)=If
If = 10.37mA
@ CPLD Vol max (0.5V) and Max forward voltage If = 8.51mA
CPLD IoL (max) = 24mA
PCB Trace Width:0.010” (0.3 A max)
270Ω was chosen as the current limiting resistor to produce a forward
current slightly above 10mA under typical operating conditions
There is no minimum current needed to drive the LED’s, but the lower the
current the dimmer the LED’s. 10mA is the ideal brightness.
65
Calculations / Component Selection
Device Package Type:
LED Forward current:
LED Forward voltage:
Source Voltage:
Current Limiting resistor:
SMT1210 LED
Typical 25mA
2V Typical, 2.6V Max
5V
(VS-VLED)/150Ω (+/-5%)=If
If = 20mA
@ CPLD Vol max (0.5V) and Max forward voltage
If = 12.7mA
CPLD IoL (max) = 24mA
PCB Trace Width:0.010” (0.3 A max)
150Ω was chosen as the current limiting resistor to produce a forward
current of 20mA under typical operating conditions
There is no minimum current needed to drive the LED’s, but the lower the
current the dimmer the LED’s. 20mA is the ideal brightness.
66
User Interface DFM
Component
8 Resistor Array
4 Resistor Array
Fixed Capacitor
7 Segment LED Display
Green LED
Component
Momentary Off Switch
Nominal
Value
270 ohms
150 ohms
0.1uF
Passive Discrete Components
Maximum
Maximum
Constant
Derated Power
Working
Current
Maximum Surge
Tolerance Capacity (mW) Voltage (V)
(mA)
Current (mA)
+/- 2%
160
50
24.6
+/- 5%
125
200
29.6
+/- 10%
50
105
8.8
25
150
65
5.6
25
100
Switching Switching
Switching
Power
Voltage
Current
Min/Max
Min/Max
Min/Max
0.02mW/3W 2V/30V
10uA/100mA
Composition
Dielectric or
Form
Package
Thick Film
16-SOM
Thick Film SMT 1206x4
Ceramic
Form
DIP-28
Form
SMT1210
Contact
Insulation
Resistance Resistance Bounce Time
<50m ohms >1010 ohms <1ms
Package
SIP
67
CPLD – Definition

This block shall maintain the safety of the device as well as the primary state control.

The block will control the transducer circuit as well as all the operator interfaces.

The block will convert the time intervals from send to echo and produce a numerical value
of depth on the user interface.

This block will also control the power state of the product via a push button input to the
CPLD
68
CPLD – Standard Requirements

Must be comparable in cost to other manufacturers (Associated)

Must be able to send depth value to seven segment displays (Associated)

Must be able to withstand glitches from other blocks (Associated)

Design to minimize battery consumption (Allocated)
69
CPLD – Performance Requirements

Must be accurate to within 5% of total depth (Associated)

Must be capable of measuring depths up to 50 Feet (Associated)

Design to work with relatively noisy signals from transducer circuit (Associated)

Design to incorporate error mode to ensure safe operation when not retrieving a signal
(Associated)

Be somewhat shock resistant for marine and portable use (Associated)
70
Block Signal Input/Output Summary
CPLD
Block Name: CPLD Block
Block Number: 2
Power Signals
To - From
Block #'s
Power1a VCC +5
From 1
Digital Signals
To - From
Block #'s
Digital1 On/Off Push Button
From 3
Digital2 English/Metric Push ButtonFrom 3
Digital 3 English LED
To 3
Digital 4 Metric LED
To 3
Digital 5 LED Display (Qty. 22)
To 3
Digital 6 Transmit Enable
To 4
Digital 7 Echo Input
From 5
Digital Signals
To - From
Block #'s
Digital1 On/Off Push Button
From 3
Digital2 English/Metric Push ButtonFrom 3
Digital 3 English LED
To 3
Digital 4 Metric LED
To 3
Digital 5 LED Display (Qty. 22)
To 3
Digital 6 Transmit Enable
To 4
Digital 7 Echo Input
From 5
Type
Direction Block-Block
Interconnect
DC Power Input
Type
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Vih Min
2V
2V
N/A
N/A
N/A
N/A
2V
Dir
Input
Input
Output
Output
Output
Output
Input
PCB Trace
5.0V
PCB Trace
PCB Trace
PCB Trace
PCB Trace
PCB Trace
Wire
Wire
.8V
.8V
N/A
N/A
N/A
N/A
.8V
N/A
N/A
Totem
Totem
Totem
Totem
N/A
Pole
Pole
Pole
Pole
IiL Max
20mA
20mA
N/A
N/A
N/A
N/A
20mA
Voltage Range
Freq
Min
Max Nominal
4.75V
Block-Block
Output
Interconnect Structure
Input Characteristics
Iih Max
ViL Max
10uA
10uA
N/A
N/A
N/A
N/A
10uA
Voltage
Nominal
Input
Structure
Standard
Standard
N/A
N/A
N/A
N/A
Standard
5.25V DC
Tech
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Freq
Logic
Nominal Voltage
DC
DC
DC
DC
DC
DC
DC
5V
5V
5V
5V
5V
5V
5V
Output Characteristics
Voh Min Ioh MaxVoL Max IoL Max
N/A
N/A
2.4V
2.4V
2.4V
2.4V
N/A
N/A
N/A
100uA
100uA
100uA
100uA
N/A
N/A
N/A
.5V
.5V
.5V
.5V
N/A
N/A
N/A
24mA
24mA
24mA
24mA
N/A
71
CPLD Block – Block Diagram
Output to 7-Segment Display
22 Sinking Outputs
22
Output to Meters/Feet LED’s
2 Sinking Outputs
2
From Power Supply
Power Input
Filtering
Power Supply to Processor
Input from Echo Receive
Circuit, 5V Logic Input
Main
Processor
CPLD
Input from User Interface
2 5V Logic Inputs
Clock
Output to Transducer Transmit Circuit
1 Sinking Output
72
CPLD – Schematic
All disconnected pins are
unused in the design. CPLD
will disregard these I/O
73
CPLD – Bill of Materials
(1) - Lattice Semiconductor CPLD – M4A5 32/64
(3) - .1 uF Ceramic Capacitors
(1) – 555 Timer National Semiconductor – LM555CN/NOPB
(1) – 2.94k Ohm Resistor Yegeo – MFR-25FRF-2X94
(1) – 100 Ohm Resistor Panasonic – MFR-25FRF-100R
(2) - .01 uF Ceramic Capacitors Epcos – B37981M1103K000
74
CPLD – Bill of Materials
Detailed Design Calculations
- CPLD Selection
Requires clock speeds above 10kHz
Requires up to 32 input/Output pins
Requires minimum of 16 Registers
*Selection based on this material, Lattice Semiconductor M4A5 line best suited for application
while still remaining a low power device
-Capacitor Selection for Power Supply Inputs
Requires .1 uF capacitance
*Selection based on this material, devices are easy to find and readily available
-Resistor Selection for Key Timing Parameters
Requires 1% accuracy
*Selection base on this material, any high accuracy resistor shall be suitable
-Capacitor Selection for Key Timing Parameters
Requires .01 uF capacitance
*Selection based on this material, devices are easy to find and readily available
75
CPLD – Bill of Materials
Detailed Design Calculations for Clock Circuit
- Required clock speed of 24.07 kHz is necessary to obtain depth accuracy at 60 °F
- 555 Timer Calculations
Generated Clock Speed Calculation
Freq = 1.44/(R1 + R2 * 2) * C
24.07kHz = 1.44/100 + 2940 * 2) * .01 e-6
- Effect of Component Tolerance Errors
Highest Frequency =
Lowest Frequency =
24.565kHz = 2% error in depth
23.608kHz = 2% error in depth
76
CPLD Theory of Operation
-
The CPLD shall control the states of the device as well as control
transmitter circuit and user interfaces
-
The depth will be figured by using multiple BCD counters in series.
The clock speed for the CPLD is configured for which each clock
pulse = 1 ft of depth.
-
The CPLD will determine the time from sending the signal to receiving
it back, this time is counted on the BCD counters and is latched to the
output LED’s once the Echo signal is received.
-
BCD Counters will also determine Timeout (S) and Timeout (L)
77
CPLD Theory of Operation
(State Diagram)
Echo Receive (OR) Timeout (L)
Idle Feet
Timeout (L)
Send Feet
Timeout (S)
Receive Feet
Units Sw.
Units Sw.
Power Sw.
Idle Meters
Timeout (L)
Send Meters
Units Sw.
Power Sw.
Units Sw.
Off
Timeout (S)
Receive Meters
Echo Receive (OR) Timeout (L)
78
DFM Analysis for Digital Devices
Output
Type
Input
Type
Tech
Type
DC Drive Device Parameters
Vil Max Vih Min Iil (-) Max Iih Max Vol Max Voh Min Iol Max Ioh (-) Min Vhyst Checked?
Component
Lattice Semi
M4A5 32/64
STD
STD
CMOS
0.8V
2.0 V
10 uA
10 uA
0.5 V
2.4 V
10 mA 3.2 uA
N/A
79
CPLD Block Passive Components
Nominal
Adjustment
Value or Max
Range,
Value
%/Turn
Tolerance
Around
Nominal
Derated
Pow er
Capacity
Maximum
Working
Voltage
Maximum
Constant
Current
Maximum
Surge
Current
Package
Component
Resistor
Resistor
Fixed Capacitor
Fixed Capacitor
2940 Ohm
100 Ohm
.01uF
.1uF
N/A
N/A
N/A
N/A
1%
1%
10%
10%
.25 W
.25 W
N/A
N/A
100V
100V
50V
50V
N/A
N/A
1206
1206
0805
0805
N/A
N/A
80
Printed Circuit Board #1
81
Printed Circuit Board #2
82
Overall Mfg Process Diagram
Screen
Print
Setup
Hand
Placement
Wash
In Circuit
Test
Placement
Stress
Screen
Reflow
Inspection
Functional
Test
Pack/Ship
83
Manual Insert Manual Solder
Through Hole
LED Display
 Momentary Off Pushbutton
 17.5 Kohm resistor
 CPLD Socket

Non PCB Mounted



D-Cell holder
Transducer
MTA Connectors
84
Depthfinder 600 Production BOM
Generic Part Name
Resistor
Resistor
Capacitor
Capacitor
Capacitor
Transformer
Zener Diode
D-Cell Battery
D-Cell Holder
Transistor
Fuse
Fuse
Transducer
MTA Connectors
Voltage Regulator
Voltage Regulator
LED Display
LED
8 Resistor Array
4 Resistor Array
Momentary Off Pushbutton
Crystal
CPLD
Capacitor
LM555 Timer Chip
Horizontal Trimmer
Resistor
Capacitor
Capacitor
Tone Decoder
Voltage Comparator
Op Amp
Resistor
Resistor
Resistor
Resistor
Resistor
Variable Resistor
Capacitor
Capacitor
Capacitor
Totals
QTY PCB Attach
4
1
4
2
1
1
2
8
2
1
1
1
1
2
1
1
1
2
3
1
2
1
1
4
2
1
1
1
1
1
1
1
2
1
1
1
1
1
2
4
2
SMT
SMT
SMT
SMT
SMT
SMT
SMT
Non PCB
SMT
SMT
SMT
Non PCB
Non PCB
SMT
SMT
TH
SMT
SMT
SMT
TH
SMT
Non PCB
SMT
SMT
TH
SMT
SMT
SMT
SMT
SMT
SMT
SMT
SMT
SMT
SMT
TH
TH
TH
TH
Package
Placement-Solder
Mfg 1
Mfg 1 Part #
DIP
DIP
DIP
DIP
DIP
DIP
DIP
Fully
Fully
Fully
Fully
Fully
Fully
Fully
Panasonic - ECG
Panasonic - ECG
Nichicon
Nichicon
Vishay
Pulse
Microsemi
ERJ-8GEYJ302V
ERJ-8GEYJ102V
F951E105MPAAQ2
F951A106MPAAQ2
2222 383 62202
BV039-5311.0
1N5383BRLOSTR-ND
Automatic
Automatic
Automatic
Automatic
Automatic
Automatic
Automatic
Man Insert - Auto Solder
Fully Automatic
Fully Automatic
Fully Automatic
Man Insert - Auto Solder
Man Insert - Auto Solder
DIP
Fully Automatic
DIP
Fully Automatic
DIP
Man Insert - Man Solder
1210 Fully Automatic
16-SOM
Fully Automatic
1206x4
Fully Automatic
SIP
Man Insert - Man Solder
DIP
Fully Automatic
TQFP
Fully Automatic
0402
Fully Automatic
DIP
Fully Automatic
Meanever
bc4d
NEC
NE685M03-T1-A
Littelfuse Inc
0451004.MR
Littelfuse Inc
0451001.MR
Panasonic - ECG
EFR-TQB40K5
Molex/Waldom Electronics Corp 39-51-3040
National Semiconductor
LM340MP-5.0/NOPB
National Semiconductor
LM2940IMP-9.0/NOPB
Lumex Inc.
LDT-A512RI
Dialight
597-3301-107F
Bourns Inc.
4816P-T01-271LF
CTS Corporation
744C08315JTR
C&K Components
K12C BK 1 2.5N
Epson
MC-405 25.60000K-A0
Lattice
M4A5-32/32-10JNI
Epcos
LLL153C80J104ME01E
National Semiconductor
LM555
Axial
Axial
Axial
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
Ohmite
Panasonic ECG
Surplus Sales
National Semiconductor
National Semiconductor
Texas instuments
Yageo Corp
Ohmite
Ohmite
Ohmite
Ohmite
CTS Corporation
AVX Corporation
AVX Corporation
AVX Corporation
DIP
DIP
DIP
Fully Automatic
Fully Automatic
Fully Automatic
Man Insert - Man Solder
Man Insert - Man Solder
Man Insert - Auto Solder
Man Insert - Auto Solder
Man Insert - Auto Solder
Man Insert - Auto Solder
Man Insert - Auto Solder
Man Insert - Auto Solder
Man Insert - Auto Solder
Man Insert - Auto Solder
Man Insert - Auto Solder
Man Insert - Auto Solder
ALSR-5-17.5K
ECJ-TVB1C103M
001000R0DDCA
LM567CN/NOPB
LM311N
LM741CN/NOPB
CFR-25JB-10K
OD105J
OD183J
OD105J
OD105J
296UD103B1N
04025A110KAT2A
5NS210KAALI-G-ND
02013J0R5PBSTR
$Cost Total
$0.01
$0.06
$0.12
$0.18
$0.31
$10.47
$0.44
$3.58
$0.39
$0.47
$0.47
$14.38
$1.04
$0.46
$0.88
$3.07
$0.50
$1.15
$0.11
$3.55
$1.23
$4.76
$0.12
$0.81
$0.00
$0.66
$0.09
$0.50
$1.80
$0.55
$0.84
$0.16
$0.42
$0.40
$0.42
$0.42
$1.51
$0.10
$0.28
$0.14
$56.84
85