Transcript FLASH memory

Emulated EEPROM Function for Data storage (ref. 908LJ12)
:
LDHX
JSR
:
DataFile2 pointer
DataFile1 pointer
CPUSPD
$<DataFile1PTR>
WRITE_EE
Block
Boundary
Control Size
Data Size
CPUSPD
Address High 2
Data Size
Address Low 2
Address High 1
Data0
Address Low 1
Data1
Data0
Control
Segment1 Segment2 Segment3 Segment4
Segment5 Segment6
LIFO
Data1
DataN
:
LDHX
JSR
:
DataN
$<DataFile1PTR>
READ_EE
RAM
•
•
•
•
The code is pre-installed in ROM and ready to use - USER FRIENDLY!
Data file can be located in any location of RAM - FLEXIBLE!
User defined data size to be programmed, 2bytes to 15 bytes at a time - FLEXIBLE!
FLASH endurance can be improved up to 60 times with 128 bytes block size.
Prepared by K.M. Fung
Internal Use Only
Segment0
8 Jan 2002
1
FLASH memory
In Circuit Flash Programming Platform (ref. 908LJ12)
DataFile1 pointer
DataFile2 pointer
CPUSPD
Data Size
Address High 1
Address Low 1
Data0
Data1
DataN
PROGRAM
CPUSPD
Data Size
Address High 1
Address Low 1
Data0
Data1
VERIFY
FLASH
:
LDHX
JSR
:
$<DataFile1PTR>
PRGRNGE
:
LDHX
JSR
:
$<DataFile2PTR>
LDRNGE
RAM
DataN
RAM
Function Name
Calling Address
Feature
WRITE_EE
$FC00
Stack the DATA segment from data file to the FLASH block and updates dirty control bit
accordingly. If block overflows, performs block erase.
READ_EE
$FC03
Read last updated DATA segment from FLASH block back to data file.
LDRNGE
$FF30
Load data from FLASH block to data file with specific location and size.
PRGRNGE
$FC06
Program specific FLASH location with data listed in data file.
ERARNGE
$FCBE
Perform mass erase or single block erase according to user selection.
ICP_LDRNGE
$FF24
Perform same operation as LDRNGE. This subroutine is specially designed to use under
monitor mode.
ICP_PRGRNGE
$FF28
Perform same operation as PRGRNGE. This subroutine is specially designed to use
under monitor mode.
ICP_ERARNGE
$FF2C
Perform same operation as ERARNGE. This subroutine is specially designed to use
under monitor mode.
Prepared by K.M. Fung
Internal Use Only
8 Jan 2002
2
HC908 Flash In System Programming through SCI Port
The window s/w allow user - Load/Upload data from MCU
- Erase/Program/Verify Flash Memory
Start
ISP?
Execute
User Code
Disable COP.
Exec. ISP Routine
Application System
TXD
SCI
RXD
RS232
Prepared by K.M. Fung
Internal Use Only
MC145407
8 Jan 2002
3
68HC908
MCU
HC908 Flash In System Programming through SCI Port
FLASH Data
$0000 I/O Registers
$0040
RAM
$023F
Application Software
FLASH Programming
Algorithm
TxD
SCI
RxD
PTA0
$8000
Erase FLASH
FLASH
ISP Routine
Prepared by K.M. Fung
Internal Use Only
$FE00
Registers
Monitor ROM
$FFFF
Vectors
8 Jan 2002
4
Programming and erasing
of FLASH locations
cannot be performed by
code being executed from
the FLASH memory
In-Circuit Programming system configuration
•
In-System Programming is a process by which the device is programmed or
erased with the device on the final end target system without open the case
of the system.
Personal Computer
Target System
Interface Board
OSC_1
Software
- MCUscribe
- ICS08
M68SPGMR08
OSC_SEL*
PA0
RS232
VPP
Additional H/W:
- Header x 1 pcs
- Diode x 2 pcs
- Resistor
- HC4066* x 1 pcs
VCC_S
GND
It may be some different control signals between interface
board and target system depends on different application
Example: GP32 and MR24/32 ICP Reference Demo board use 4 wires (PA0, Vpp, Vcc_s and GND).
Remark: OSC_SEL and HC4066 is used when the oscillation frequency of target system is not equal to the oscillation
frequency which required to entry to the monitor mode of the MCU.
Prepared by K.M. Fung
Internal Use Only
8 Jan 2002
5
GP32 In-Circuit Programming Reference Demo
GP32 Target board simulates a typical
application, user running code will be
executed after provided the power to
the board (rurns the LED on and off
repeatedly)
Prepared by K.M. Fung
Internal Use Only
Remove the Target Board power and then
upgrade the firmware through four wires
and SPGMR with PC
8 Jan 2002
6