Transcript watson_sid_15apr2008 - Elementary Particle Physics

MAPS ECAL
SiD Workshop
RAL 14-16 Apr 2008
Nigel Watson
Birmingham University
 Technical Status
 Future Plans
 Summary
For the CALICE MAPS group
J.P.Crooks, M.M.Stanitzki, K.D.Stefanov, R.Turchetta, M.Tyndel, E.G.Villani
(STFC-RAL)
J.A.Ballin, P.D.Dauncey, A.-M.Magnan, M.Noy (Imperial)
Y.Mikami, O.D.Miller, V.Rajovic, NKW, J.A.Wilson (Birmingham)
MAPS ECAL: basic concept
Weighted no. pixels/event
• Swap ~0.5x0.5 cm2 Si pads with small pixels
• “Small” := at most one particle/pixel
• 1-bit ADC/pixel, i.e. Digital ECAL
• How small?
• EM shower core density at
500GeV is ~100/mm2
• Pixels must be<100100mm2
• Our baseline is 5050mm2
• Gives ~1012 pixels for ECAL –
“Tera-pixel APS”
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Effect of pixel size
50mm
100mm
>1 particle/
pixel
Incoming photon energy (GeV)
Nigel Watson / Birmingham
New since Jan. workshop?
What is it sensible to show?
Results from testbeam??
Hints that we are starting to understand
what is going on?
JB evt display? Layer-layer correlation
plots a la TM?
Etc?
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CALICE INMAPS TPAC1
First round, four architectures/chip
(common comparator+readout logic)
0.18mm feature size
INMAPS process: deep p-well
implant 1 μm thick under electronics
n-well, improves charge collection
4 diodes
Ø 1.8 mm
Architecture-specific
analogue circuitry
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The CALICE TPAC1
 50x50 mm cell size
 Comparator per pixel
 Capability to mask individual pixels
 4 Diodes for ~uniform response w.r.t threshold
 13 bit time stamp (>8k bunches individually tagged)
 Hit buffering for entire bunch train (~ILC occupancy)
 Threshold adjustment for each pixel
 Usage of INMAPS (deep-p well) process
[Marcel Stanitzki]
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TPAC1 overview
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8.2 million transistors
28224 pixels; 50 microns; 4 variants
Sensitive area 79.4mm2
“region”
Four columns of logic + SRAM
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Logic columns serve 42 pixels
Record hit locations & timestamps
Local SRAM
11% deadspace due to readout/logic
Data readout
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Slow (<5 MHz)
Current sense amplifiers
Column multiplex
30 bit parallel data output
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“Group”
(region=7 groups of 6 pixels)
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Attention to detail 2: beam background
 Beam-beam interaction by
GUINEAPIG
 LDC01sc (Mokka)
purple = innermost endcap radius
500 ns reset time  ~ 2‰ inactive pixels
y (mm)
 2 machine scenarios studied
:
 500 GeV baseline,
 1 TeV high luminosity
Study to be repeated in SiD01
X (mm)
Verify optimisation
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[O.Miller]
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Progress with sensor tests
Work ongoing to test unformity of threshold and gain
Report today on testbeam
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Hit buffering for train
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MAPS testbeam
 Desy 10-17 Dec. 2007
 Extremely tight schedule…
 4 sensors, PMT coincidence trigger
 3, 6 GeV e With/without tungsten pre-shower material
 Threshold scans
 USB_DAQ
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PMT trigger
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Sensor setup in testbeam
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Concentrate on shapers
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Strategy
Want to start with the highest purity
sample we can
Scintillators behaviour “not optimal”
Ensure sensor hits genuine
 Use clusters of hits initially, not single
pixels
Can we match clusters between sensors?
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Clustering
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Layer-layer correlations: x
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Layer-layer correlations: y
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Layer-layer alignment
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…and funding
Recognised as generic technology
Much interest to continue development of
concept for ECAL
 Including for SiD
…
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MAPS summary
 Concept of CMOS MAPS digital ECAL for ILC
 Multi-vendors, cost/performance gains
 New INMAPS deep p-well process (optimise charge
collection)
 Four architectures for sensor on first chips,
delivered to RAL Jul 2007
 Tests of sensor performance in progress: sources,
charge diffusion, cosmics, testbeam
 Physics benchmark studies, compare MAPS vs.
analogue Si-W designs
 In framework of SiD and IDC detector concepts
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Summary
 MAPS ECAL: alternative to baseline design (analogue SiW)
 Multi-vendors, cost/performance gains
 New INMAPS deep p-well process (optimise charge
collection)
 Four architectures for sensor on first chips
 Tests of sensor performance ongoing
 Physics benchmark studies with MAPS ECAL to evaluate
performance relative to standard analogue Si-W designs,
for both SiD (and ILD) detector concepts
 Future plans
 Systematic studies of pixel to pixel gain and threshold
variations
 Absolute gain calibration
 Second sensor…
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Backup slides…
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Architectures on ASIC1
Presampler
Preshaper
Type dependant area: capacitors, and big resistor or monostable
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