Transcript LECC2006_state_of_art_hybrids - Indico

CERN
TS-DEM
Development of Electronic Modules
State of the art technologies
for front-end hybrids
Rui de Oliveira
CERN
Rui de Oliveira
TS-DEM
CERN
Contents
1. Existing technologies
2. Pitch adaptors
3. Trends in future circuit materials
4. Cooling
5. Low mass
6. Buried components
7. Conclusions
Rui de Oliveira
TS-DEM
CERN
1. Existing technologies
Minimum line and space
20μm
25μm
Thin film hybrids
50μm
75μm
90μm
MCM/D (deposited)
MCM/C (ceramic)
HDI circuits / SBU / MCM/L (laminated)
Thick film hybrids
120μm
PCB
Organic technologies
Mineral technologies
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HDI Laser micro via process
Cu
dielectric
Glue
Metallization
Cu
N-1
Laser Copper
Etching
Plasma Cleaning
Dielectric Laser
Ablation
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2. Pitch adaptors
State of the art in HDI Hybrids:
Minimum line and space 40 to 75 μm  80 to 150 μm pitch
45 μm pitch is often required to connect front end chips
This fine pitch is not needed in the whole circuit
Use a denser technology?
Introduce a thin film pitch adaptor?  delicate assembly
Build the pitch adaptor in MCM/D?  not cost effective in
many cases because the whole circuit will be produced with
a high density technology
Split the dense area in multi layers in MCM/C or HDI
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Pitch adaptor technologies
Pitch adaptor Al on Glass
Minimum line and space: 15 μm
one layer
Minimum pitch: 30 μm
Pitch adaptor on thick film Hybrid
Minimum line and space: 40 μm
2 or more layers
Minimum pitch: 25 μm (3 layers)
Pitch adaptor on HDI
Minimum line and space: 40 μm
2 layers
Minimum pitch: 40 μm (2 layers)
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Advantages of HDI built in pitch adaptors
•
•
•
•
•
Reduced cost
Already in the circuit: no need for post assembly
Thin thicknesses: down to 100 μm
Low Dk and low loss materials
Any shape is possible: not limited to parallelograms
like in Thin film or Thick film
• Larger bonding pads
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3. Trends in future circuit materials
Board
manufacturability
Reliability
Environmental
friendly
Functionality
Miniaturization
Process
compatibility
Low CTE
Halogen free
Low Dk
Embedded
Fillers
Lead Free
Low Df
Metal core
Registration
High TG
Drilling
compatibility
Embedded
CAF-resistant
CAF: conductive anodic filament
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Commonly used dielectrics
• Glass epoxy: FR4, Halogen free, High Tg, Z CTE
control, low Df, CAF resistant
• RCC: “Resin coated copper”
• Polyaramid/epoxy: Thermount, kevlar epoxy
• Glass polyimide
• Polyimide
• LCP (liquid crystal polymer)
• PTFE: pure, PTFE fiber + epoxy, Glass fiber + PTFE
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4. Cooling
CERN
CTE
[Ppm/deg C]
Thermal
conductivity
[W/m.deg C]
Process
Price
CIC
5
170
easiest
low
Aluminium
22
220
easy
low
Al/ Si
6-15
120
easy
medium
Carbon fibre
2
Up to 1000/z 10
difficult
medium
Carbon carbon
2
600/z 300
difficult
high
PG
0
600/z 8
difficult
high
TPG
0
1600/z 8
very difficult
very high
Alumina
7
22
easy
low
Berylia
8
300
easy
high
AlN
4
100-230
difficult
medium
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Possible structures
• Buried: CIC, Aluminium and ceramics (Thick film)
• Glued to the circuit: all of them
• For better reliability:
– CTE close to Silicon (from 2 to 10 ppm)
– Be careful with non-isotropic CTE or high-CTE materials
– Use of high-TG materials
– Use of elastic glues with big CTE mismatch
– Be careful with adhesion to carbon structures
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Thermal simulation
LHCb
PS/SPD
CERN TS/CV
Computational Fluid Dynamics team
www.cern.ch/cfd
[email protected]
Tools:
Flotherm
Star CD
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5. Low mass
Material
Radiation length
[cm]
Density
[gr/cc]
Resistivity
[uohms*cm]
Aluminium
8.9
2.7
2.7
Copper
1.4
9.0
1.7
Beryllium
35.3
1.9
3.3
Gold
0.3
19.3
2.4
Glass epoxy
19.4
Polyimide
29.0
• Copper is close to 6.5 times less transparent than aluminum
• Aluminum has only 1.6 times the resistivity of copper
• Polyimide is 1.5 times better than glass epoxy
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Alice Pixel Bus
MCM
PIXEL BUS
Signals2
Signals3
Signals1
VDD
Signals3
Signals2
Signals1
GND
VDD
GND
Pixel detector
Pixel readout chip
3 signal layers and a
staircase shaped side
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Aluminium bus details
Aluminium bus for
Alice Pixel detector
Size: 160 mm x 16 mm
Working support
Thick Cu (300 μm)
Chemically removed
after finalisation of circuit
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Aluminium Micro-vias Process
Vacuum Al
deposition
Cu
Polyimide
Glue
Al
Metallization
Copper etching
Copper Etching
Dielectric Etching
Anisotropic
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Glue Etching
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12 microns vacuum deposited aluminium
Bonding close-up view
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6. Buried components
• Resistors
• Capacitors
• Active devices
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Buried resistors:
“Omega ply” or “Gould TCR”
Integrated resistor benefits
Increases density, no via, no solder joints
Reduce PCB assembly
Improves impedance matching
Reduces series inductance
Reduces crosstalk and noise
Resistor value and stability
Better than ± 10%
Laser trimmable down to ±1%
Stability : -20, 100 or 200 ppm
Drawbacks
Few suppliers and manufacturers
No resistor change possible after layout
Resistor values limited (25 to 250 ohms/square)
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Buried capacitors
• Thin dielectrics
– conventional thickness of 55 μm reduced to 10 μm
– dielectric loaded with particles of ceramic or barium compounds
• Dielectric constant
– ZBC2000™ (Sanmina Corp): 4.0
– BC16T (OAK-MITSUI): 30
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• Value
– 155pF to 1.7nF/cm2
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Buried active devices
Technology
thin chips (50 μm or thinner)
embedded in RCC layer
thickness = 70 –100 μm
Contact to the chip by laser microvia
and Cu metallisation on chip
Challenges
Process control (die bond thickness)
Contact to the chip
“large area” processing
Reliability Multilayer Build-up
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7. Conclusions
• HDI technology is currently the best candidate for HEP front
end electronics
• It is possible to boost this technology in local areas
• A lot of dielectric materials exist but not all companies have
the know how
• Thermal management: simulate!
• HDI low mass: limited number of producers,
CERN is ready for small to medium volumes
• Buried passive components is a real possibility in the near
future. Buried active further away (is there a real need in HEP?)
www.cern.ch/dem
Rui de Oliveira
TS-DEM