Transcript Class2_21_lab and project assignment

Lab and Project Assignments
12/4/2002
2
Lab Assignment: Clock skew and jitter measurements
 Hand PPT lab report.
 Activities:
Locate clock probe points on layout.
Measures skew (at CPU0, CPU1, both P64H2s, MCH, and
ICH) and Jitter at MCH.
 PPT minimum contents
Hypothesis: What you are measuring and why it is
important.
Results Summary: Jitter and Skew
Supporting data:
Illustrate where probes are placed
Describe complete scope setup and threshold assumptions.
Show all clock waveform super imposed on one graph.

Determine skew from this

Describe issues with this simple jitter method.
Show simple jitter (infinite persistence) include picture of
jitter.
Introduction
12/4/2002
3
Project Assignment: Simulation to Lab Correlation
 Goal: Tune simulations to measurements
 Activities:
Locate DDR signal being probed.
Determine all segments and component value.
You may need to get component values from examining the board.
Measure necessary DC voltages
Modify the HSPICE DDR template file with actual values.
Probe points
One probe is on a data signal on the DIMM before the series resistor (End closest to DRAM chip)
The other probe is on a the same data signal at the MCH.
Capture a read signal at the MCH.
Compare measured signal to simulated signal. You may need to bring into a spreadsheet and
time shift data to get to over lap.
Adjust elements in the simulation model achieve reasonable agreement with measurements.
You need to define what reasonable is and justify that.
 PPT minimum contents
Hypothesis: Simulation model accurately predict real circuits.
Results Summary:
Overlay of simulation and measurement waveforms.
Overivew of component changes that had the most effect on achieving the best results.
Supporting data:
Illustrate where probes are placed
Describe complete scope setup and threshold assumptions.
Show you circuit diagram and slides to illustrate changes. For example you may need W elements for
transmission lines or you may not. Inductor and cap values may need to be altered.
Introduction
12/4/2002
4
Starter Schematic For DDR Simulation
0/2. 7V
7.8pf
7.8pf
1.2nH
1.2nH
ZO=55
160ps
22
133MHz
0.6nH
ZO=55
160ps
ZO=55
160ps
22
3.25pf
3.25p
0.6nH
ZO=55
160ps
.15pF
10
22
.15pF
22
.15pF
.15pF
4.5nh
4.5nh
4.5nh
4.5nh
.3pF
.3pF
.3pF
.3pF
184.96ps
184.96ps
184.96ps
62. 04ps
ZO=51
ZO=51
ZO=51
ZO=51
39. 1
10uF
+
1.15V -
250
202ps
229.35ps
229.35ps
ZO=50
ZO=48
ZO=48
+
2.7V
-
3.03p
69. 3ps
0.35nH
0.05pf
ZO=51
10
0.05pF
.01pF
Introduction
12/4/2002