Transcript Thin Film Overview

Introduction to CMOS
Process Integration
OVERVIEW: PRODUCT CATEGORY
2005 Global market size = RM 235 billion
%
5
9
16
Opto-electronics
Discrete
Analog
• Exotic processes involved; should reconsider as capability increases
• Low margin and scale wins in discrete market;
•
•
•
Fragmented market with no dominant player
Higher margin, especially in niche market
Longer shelf life (~15 years) compared to digital technology
• Design dominated by leading design houses
• Scale wins in fabrication, dominated by 3-5 largest global foundries
• Heavy R&D on deep sub-micron technology required
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Logic
21
Memory
• Intense competition, top 5 players have > 70% market share
• Low ROIC, large scale require to play
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MPU
• Dominated by Intel, AMD, Motorola and IBM
• Continuous large R&D investment required
= 100
Source: IDC
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OVERVIEW: TECHNOLOGY
2005 ITRS Conclusions;
Despite significant technology challenges, the industry continued to maintain the pace predicted by
Moore's Law - the doubling of transistors every two years.
Transistor speed continued to improve at the historical improvement rate of 17 percent per year, although
the challenges became more complex due to a concurrent increase in leakage currents.
Research intensified on major technology innovations like high-k dielectrics, metal gate electrodes, and
multiple-gate MOS transistors, which are forecast to enter manufacturing before the end of the decade.
These represent major shifts, where some basic device materials and structures will undergo change for the
first time in more than 30 years.
Mixed-signal and analog chips continue to grow in importance, driven especially by consumer and
communications-related markets.
State-of-the-art microprocessors now run well in excess of several GHz. Memory designs are geared
increasingly to specific applications. And new memory technologies based on totally new concept
(spin state, molecular and single electron memory are emerging)
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BUSINESS MODEL
 Foundry (TSMC, UMC, Silterra, 1st Silicon)
– only manufacture
 Design House (Alterra, MyMS)
- only design
 Integrated Design Manufacturing (Intel, Motorola, IBM,
MIMOS)
- design and manufacture
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Semiconductor Manufacturing Processes
 Design
Mask info to MASK-SHOP +
GDSII file
 Mask making
 Generate runcard
 Wafer Preparation
 Front-end Processes (individual
transistor)
Deposition
Oxidation
Diffusion
Photolithography
Etch (wet and dry)
Implantation
 Backend Process





Deposition (oxide, nitride etc)
Metalization
Rapid Thermal Process
Lithography & Etch
 Test (Parametric and Functional)
 Packaging
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Circuit
Schematic
VDD
S
Layout
Silicon
VIN
Poly
gate
pMOS
vDD
D
VIN
pMOS
VOUT
D
p+
drain
p+
source
nMOS
S
VSS
n+
drain
VOUT
n+
source
nMOS
vSS
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SILICON COMPONENTS FOR INTEGRATION
• Contacts
• Resistors
• Capacitors
• P-N Junctions
• Bipolar Transistors
• Uni-polar Transistor (FET)
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CONTACTS
• Are made to connect components to the outside world
• Bad contacts are
carriers
•Non-ohmic, high resistive
•Leaky
• Bad contacts can cause circuit failure
• Main causes for non-ohmic behavior
•Contaminated interface
•Incomplete contact etch
•Low dopant concentration (dopant depletion from
Si into silicide
• Main cause for leaky behavior is metal penetration (Al spiking)
• Characterized by a parameter called contact resistance
(ohm per contact) using test structure called contact chain.
Several thousands of contact of different sizes running
on different topography.
Height of barrier
to carrier flow
ILD0
AlSiCu
GATE
Silicon
ILD0
AlSiCu
GATE
Silicon
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CONTACTS (continue)
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CONTACTS (continue)
I
• Ohmic Contact
• Formed between metal and heavily doped Si
• Barrier exist but is very thin
• Carriers tunnel through the carrier
• Symmetrical I-V characteristics
Non-ohmic
V
• Non-ohmic behavior
• High contact resistance
• Indication of process problem or bad integration
• Schottky barrier
• Formed between metal and lightly doped Si
• Wide barrier
• Diode I-V characteristics
ohmic
I
forward
BV (>20V)
V
Vt (0.3-0.8V)
reverse
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RESISTORS
• Applications
• Analog mixed signal (RF & wireless application), when high precision
and matching were needed.
• Current limiter
• Voltage drop
• Diffused layer (nwell ~ 1000 ohm per square) and poly-1 (~ 35 ohm per square)
normally used as resistors
• Parasitic resistance
• transistor / IC speed degradation: RC delay
• Source and drain region (salicide, halo implant)
• Contact and via (silicide)
• Metal lines (copper)
LOCOS
substrate
Poly as resistor
substrate
Diffused layer as resistor
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Resistivity
• Resistivity of n-type material is inversely proportional to donor concentration, ND
• µn is electron mobility
ρ = 1 / q µn ND
• Resistivity of p-type material is inversely proportional to donor concentration, NA
• µp is hole mobility
ρ = 1 / q µp NA
• As the temperature increases, the mobility decreases and resistivity increases
• shorter carriers mean free path due to lattice atoms vibration
• For the same doping and concentration and temperature, electrons are approximately
3 times mobile (faster) than holes – hence NMOS is 3 times faster than PMOS
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Resistance & Sheet Resistance
• The resistance of a resistor depends on its resistivity, length and cross-sectional are
R=ρ L/A
• Sheet resistance is the most widely parameters. Is defined as the resistance between two
opposite sides of a square of the layer. Unit: ohm / □
Rs = ρ / t
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Resistance & Sheet Resistance (continue)
Typical resistor TOP-VIEW (layout)
RESISTOR
W
L
R = Rs x L / (W – ΔW) + 2 x Rc / (W – ΔW)
Rs – Sheet resistance of resistor
L - Drawn resistor length
W – Drawn resistor width
ΔW – width reduction due to litho / etch
Rc - contact resistance
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CAPACITORS
• Applications
• Memory and logic (DRAM, E/EEPROM memory cell)
• Precision analog design
• MOS process characterization
• Device characterization, SPICE model extraction and etc.
• Parasitic capacitance
• transistor / IC speed degradation: RC delay
• Low-k dielectrics
• Thick ILD
• Good backend planarization (global planarization)
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CAPACITORS
Conductor-1
t
Insulator
Conductor-2
C = A ε0 εi / t
C – capacitance (F)
A – area common to plates (cm2)
ε0 - universal constant (8.86 x 10-14 F/cm)
εi - dielectric constant (oxide=3.9, nitride=7)
t - dielectric thickness (cm)
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CAPACITORS (continue)
MIM Capacitor (Metal – Insulator – Metal)
TiN, Al
t
Oxide or nitride
TiSi2, Al
TiN
TiSi2
Poly
FOX
Parasitic capacitance
Silicon substrate
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CAPACITORS (continue)
MIM Capacitor (Metal – Insulator – Metal)
TiN
TiSi2
Poly
FOX
Parasitic capacitance
Silicon substrate
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CAPACITORS (continue)
MIS / MOS Capacitor (Metal – Insulator – Silicon)
Poly, Metal-1
t
Oxide or oxynitride
n-type or p-type Si
S/D
n-well
GateOx
FOX
substrate
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PN JUNCTION
Xd
P-type
+
+
+
-
N-type
NO BIAS
• A pn junction is the boundary between p-type and n-type silicon
• Region between n and p is depleted from electrons and holes
• Xd is width of depleted region
• Depletion region is wider in a lighter doped region.
Given NA = 1015 cm-3, ND = 1017 cm-3
For n-type region
n=1017 cm-3 (why?)
What is p (hole concentration)?
For p-type region
p=1015 cm-3 (why?)
What is n (e concentration) ?
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PN JUNCTION (continue)
I
I
forward
+
P
-
V
Vt (0.8-1.0V)
N
reverse
• forward bias – large current
• electrons are injected into p
• holes are injected into n
• reverse bias – small current
• electrons are extracted from p-side to n-side
• holes are extracted from n-side to p-side
V
forward
I
P
+
V
N
reverse
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PN JUNCTION (continue)
A
A
Effect of resistance
10-2
10-2
avalanche
breakdown
10-5
10-5
IF
IR
10-8
10-8
10-11
Threshold swing
> 60mV / decade @ 25C
10-14
V
1
VF
2
10-11
impact
ionization
leakage
V
10
20
VR
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PN JUNCTION (continue)
P
N
p+
FOX
FOX
n-well
substrate
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MOSFETs
N-source
4 types of MOSFETs
• NMOS
• enhancement mode (normally off)
• depletion mode (normally on)
• PMOS
• enhancement mode
• depletion mode
P-well or
P-substrate
GATE
N-drain
NMOS
P-source
• Mode of operation
• To turn on: inversion layer connects S and D
• To turn off: no inversion between S and D
• Enhancement mode
• Inversion layer is initially absent. To turn on, apply
• Positive voltage on gate of NMOS
• Negative voltage on gate of PMOS
n-well or
n-substrate
GATE
P-drain
PMOS
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MOSFETs
LAYOUT
Active Region
SOURCE
DRAIN
WD
LD
Poly
Metal-1
Contact
Poly extension over LOCOS
Important Note: ALL the dimensions must FOLLOW the
Design Rules
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MOSFETs
CROSS SECTION
SOURCE
DRAIN
WD
CUT
LD
PMD or ILD0
LOCOS encroachment
into active
Leff
Spacer – for LDD (to suppress
the hot electron effect)
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MOSFETs
HOW AN ENHANCEMENT MODE NMOS WORKS
ground
VD
VG
A
PMD or ILD0
N+ Drain
Leff
N+ Source
• With 0 or negative bias on gate, there is no S to D current
• With +ve voltage on gate, holes are repelled and e attracted to the surface
• With sufficient VG, thin sheet of electron forms between S and D
• S and D are now connected
• Thin sheet of electrons is called inversion layer
• Sufficient VG is called Threshold Voltage, VT
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MOSFETs
HOW AN ENHANCEMENT MODE PMOS WORKS
ground
VD
VG
A
PMD or ILD0
P+ Drain
Leff
P+ Source
• With 0 or positive bias on gate, there is no S to D current
• With -ve voltage on gate, electrons are repelled and holes attracted to the surface
• With sufficient VG, thin sheet of holes forms between S and D
• S and D are now connected
• Thin sheet of holes is called inversion layer
• Sufficient negative VG is called Threshold Voltage, VT
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MOSFETs
TYPICAL CMOS CROSS SECTION
NMOS and PMOS on the same die to form a basic design block for VLSI technology (inverter). Superior than
NMOS or PMOS process technology in terms of;
• Lower power dissipation
When Vin is high
When Vin is low
• Design flexibility
• PMOS is off
• PMOS is on
Vin
• Compact ability
• NMOS is on
• NMOS is off
• Noise immunity
• Vout is at ground
• Vout is at Vdd
Vout
Vdd
Ground
FOX
DRAIN
nLDD
pwell
NMOS
DRAIN
pLDD
nwell
PMOS
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CMOS PROCESS INTEGRATION
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Unit processes, modules, integration
• Unit processes development
•Oxidation, deposition, lithography
•Etch, diffusion, ion implantation
• Modules development
•Gate stacks, well, isolation, source & drain
•IMD, contacts / interconnect
• Integrated Process
•CMOS, BiCMOS, EEPROM
•Flash, SRAM, DRAM
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TYPICAL CMOS PROCESS FLOW
Main Process Modules (CMOS 1P2M 3.3V)
1.
Wells Formation
2.
Active Area Definition
3.
Device Isolation (LOCOS)
4.
Vt Adjust
5.
Polygate Definition
6.
Source & Drain Formation
7.
Pre Metal Dielectrics Deposition (PMD)
8.
Contact Definition
9.
Metal-1 Deposition & Patterning
10. Inter-Metal Dielectrics Deposition (IMD)
11. Via Definition
12. Metal-2 Deposition & Patterning
13. Passivation
14. Pad Definition
FRONT END PROCESS
(creating an electrically isolated devices)
BACK END PROCESS
(connecting the devices to form the desired
circuit function.)
Full integration may require 300-500 process steps
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DEVICE ISOLATION TECHNOLOGY
• Electric circuit in VLSI technology is implemented by connecting isolated devices through specific
conducting path.
• To fabricate monolithic ICs, electrically isolated devices must be created in the silicon substrate.
• Only later they are connected.
• Improper isolated device will result;
• total circuit failure
• high leakage (large dc power dissipation)
• noise margin degradation
• voltage shift, cross talk between transistors and etc.
• The challenge is VLSI device only allows single transistor leakage < 10 pA/um). On the other hand, process
integration imposed a stringent requirement on the isolation technology;
• spacing between actives should be as small as possible
• to produce the surface topography as planar as possible
• isolation process module must be simple to implement and easy to control
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DEVICE ISOLATION TECHNOLOGY
MOS Device Isolation Characteristics
MOS transistors are self isolated as long as;
•
The source-substrate and drain-substrate pn junctions are held at reverse bias
•
Reverse bias drain-substrate leakage should be negligible
•
Insignificant drain-source current during OFF state
•
Parasitic channels are prevented from forming among adjacent devices
•
Negligible leakage current between adjacent MOS devices
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DEVICE ISOLATION TECHNOLOGY
MOS Device Isolation Characteristics
•
•
VTF is the threshold (minimum) voltage to turn on the parasitic MOS (field transistor)
2 methods of increasing the VTF;
•
making a thicker field oxide
•
Increase the doping beneath field oxide (channel stop implant)
Field transistor
M-1
DRAIN
NMOS#1
SOURCE
NMOS#2
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DEVICE ISOLATION TECHNOLOGY
Isolation technique in CMOS
•
Grow and etch thick oxide
•
Semi recessed LOCOS
•
Conventional
•
Poly buffered
•
SILO and etc
•
Fully recessed
•
Trench
a) Grow and Etch
oxidation
oxidation
nitride removal
nitride removal
b) Semi recessed LOCOS
c) Fully recessed LOCOS
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DEVICE ISOLATION TECHNOLOGY
A)
Grow and etch (used until late 70s)
•
•
Thick oxide is grown thermally in the furnace
Wafer is patterned and etch
Disadvantages
•
•
Sharp corners, difficult to cover in the latter
process steps
Channel stop must be implanted before oxide
is grown (active to be aligned with channel stop
region – low packing density)
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DEVICE ISOLATION TECHNOLOGY
B)
Semi-recessed LOCOS
Conventional LOCOS
•
20-60nm oxide is grown [pad oxide]-to cushion stress
of nitride
•
100-200nm CVD nitride is deposited as oxidation
mask. Nitride is very good in this as oxygen and
water vapor diffuse very slow through it. But
very high tensile stress
•
Mask to define active regions
•
Channel stop implant – desirable to implant after
LOCOS oxidation
•
Grown thick oxide using wet oxidation
•
Boron segregation and lateral diffusion
•
Bird’s beak
•
Strip oxide and nitride using wet etch
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DEVICE ISOLATION TECHNOLOGY
C)
Advance Semi recessed LOCOS
a)
•
•
Etch back LOCOS
The simplest way to reduce bird’s beak
A portion of LOCOS is etched after oxidation
b) Poly buffered LOCOS
•
Use thinner pad oxide [poly 50nm,oxide 10nm]
and thicker nitride
•
Solve the bird’s beak issue, do not solve
planarization.
D)
Fully recessed LOCOS
Quiz: Write an essay on a Fully recessed LOCOS isolation technology used
in CMOS wafer fabrication process.
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DEVICE ISOLATION TECHNOLOGY
Integration Issues with Thermally Grown Oxides
•
•
•
•
•
•
•
•
Contamination, ionized impurities
Bulk & interface traps
Pinholes
Uniformity
Thermal budget
Induced defects
Impact on dopant profile
Stress
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DEVICE ISOLATION TECHNOLOGY
E) Trench Technology
4 major applications
•
Locos replacement for isolation within the well
•
Isolation in bipolar
•
Latch prevention in CMOS
•
Trench capacitor in DRAM
3 categories
•
Shallow trench <1 um
•
Moderate 1-3 um
•
Deep >3um deep
Trench etched
CVD oxide deposited
Advantages
Increase the packing density tremendously
Disadvantages
Complex to fabricate, very expensive machines
Poor uniformity
Low throughput
Oxide polished to surface
by CMP
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MULTI LEVEL INTERCONNECT
TECHNOLOGY
The requirement is to connect the device electrically at the later stages of wafer
fabrication in order to implement the desired circuit functionality.
2 major components
•
Multilevel Metallization
•
Multilevel Dielectrics
WHY MULTILEVEL INTERCONNECT???
Contribute to ~75% low yield problem
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MULTI LEVEL INTERCONNECT
TECHNOLOGY
Nomenclature in IC Application
passivation
BPSG
metal
gate
FOX
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MULTI LEVEL INTERCONNECT
TECHNOLOGY
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MULTI LEVEL INTERCONNECT
TECHNOLOGY
MULTILEVEL METALIZATION
General Requirement





Low resistance materials
Low contact resistance
Electrically stable
Good step coverage (bottom and sidewall) for non plug process
Process compatibility and cost effective

Stress

Adhesion to oxide

Electro migration

Easiness to pattern and etch
good
Film
W
bad
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MULTI LEVEL INTERCONNECT
TECHNOLOGY
Materials and Application
Material
Application
Technology
(m)
ρ (-cm)
5000A
Al, AlSiCu
Interconnect
1.0, 0.5, 0.35
2.65
Cu
Interconnect
0.25, 0.18
1.67
Ti
Adhesion (Al, Cu)
0.5, 0.35, 0.25
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TiN
Barrier, ARC
0.5, 0.35, 0.25
25
TiW
Adhesion (W)
0.5, 0.35, 0.25
75
W
Via Plug
0.5, 0.35
6
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MULTI LEVEL INTERCONNECT
TECHNOLOGY
General Conclusions



Aluminum still the metal of choice

High conductivity

Process compatibility
Al drawback

Electro migration due to small grain size. Add copper (1-1.5%)

Incompatible with >500C process
Copper

Higher conductivity than Al

Better electro migration resistance

Difficult to etch. To use other difficult technique (damascene process)
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MULTI LEVEL INTERCONNECT
TECHNOLOGY
MULTILEVEL DIELECTRICS
General Requirement









Ability to electrically isolate two levels of metal
Ability to planarise, minimize the possibility of open circuits for the
subsequent metal
Chemical and thermal stability during subsequent process step
Repeatable and reliable
Good adhesion to underlying layers
Ability to produce layers of varying thickness
Process compatibility
Deposition temperature
Low k
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MULTI LEVEL INTERCONNECT
TECHNOLOGY
MULTILEVEL DIELECTRICS
Dielectric Materials




CVD oxide
PECVD oxide / nitride
SOG
Polyimide
400C
200C
27C , 450C cure
27C, 400C cure
Planarization Methods


Deposit and etch-back
Deposit and CMP
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MULTI LEVEL INTERCONNECT
TECHNOLOGY
Major Reliability Issues
Metalization
• electro migration
• stress
• corrosion
ESD
Latch-up
Transistors
• hot carrier effects
Junctions
• leakage, shorts
Dielectrics
• leakage
• breakdown, surface states, traps
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FUTURE TRENDS/ISSUES IN INTEGRATION
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FUTURE TRENDS/ISSUES IN INTEGRATION
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