Transcript F_Machefert_260309_2 - Indico

Summary of the Barcelona Meeting
March 10th and 11st , 2009
Calorimeter Upgrade Meeting
Frédéric Machefert
On behalf of the Barcelona and Orsay Groups
Albert Comerma, Carlos Abellan, Christophe Beigbeder, David
Gascon, Eduardo Picatoste, Eugeni Graugès, Frédéric
Machefert, Jacques Lefrançois, Jordi Riera, Lluis Garrido,
Olivier Duarte
Thursday 26th March 2009
Meeting at Barcelona
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The meeting took place at Barcelona on March 10th and 11st 2009
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2 sessions :
 Analog electronics
 Digital electronics
Slides and Minutes are available from
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http://indico.cern.ch/conferenceDisplay.py?confId=54924
Thursday 26th March 2009
Calorimeter Upgrade Meeting
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Analog electronics specifications (I)
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Specifications and comments
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The transverse energy range should be 0-10GeV/c on 12 bits ADC
Clipping is probably needed to have a plateau, otherwise sampling would be
done on a slope of the integration curve and the measurement would be very
sensitive to particle time arrival
 Gaussian shaping could also be studied
The PMT gain should be reduced by a factor 5 with respect to the current gain
 The electronics gain should be increased accordingly
Noise requirement corresponds to ~1ADC count or ~5fC (25/5 fC)
 A clipping at the PMT base means 25Ω in parallel to 50Ω
 This resistance determines the current to voltage conversion and as it
becomes small a low noise preamp is needed (<1nV/Sqrt(Hz))
 The possibility to have the clipping on the FEB after the pre-amplifier is
to be looked at
 Having the amplifier on the base would induce a large intervention on the
detector and has some radiation tolerance implications
The pre-amplifier should have a well controlled input impedance
 In case of clipping on the base an active termination is needed. A resistor
would induce too large a noise and an active line termination circuit would
accurately set the input impedance.
Thursday 26th March 2009
Calorimeter Upgrade Meeting
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Analog electronics specifications(I)
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AC coupling could be used thanks to the dynamic subtraction. With DC coupling
part of the dynamic is swallowed by the pedestal.
The radiation tolerance should reach 10 or 20 krad in 5 years
In order to reduce the space used and be able to integrate the optical outputs,
groups of 8 channels are desirable.
A rough (gu)estimation leads to a cost <25€ per channel
Thursday 26th March 2009
Calorimeter Upgrade Meeting
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Switch versus Delay line solutions
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Switch induces a large pedestal. Its stability could be an issue although on
the SPD this was not a problem
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Gain of the two subchannels of the switch may be different
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Switch on SPD removes ~30% of the dynamic (DC). This range should not
exceed 5% on the ECAL (done with AC coupling)
Pedestal has two origins :
 Component mismatch : a constant of the system and the dominant source
 Switch charge injection and integrator
Solutions envisaged :
 AC coupling would solve the problem of the reduced dynamics
 The AC coupling time constant should be more than 5ms not to be
sensitive to the bunch gap
 DC coupling with pedestal compensation (DAC integrated ?)
Digital correction could be necessary (how many bits ?)
But switch advantages :
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Highly integrated
Available latching time of the integrator is almost 25 ns
 This permits to have a multi-channel ADC with a single clock
The sampling plateau should be wider than with a delay line integrator
Thursday 26th March 2009
Calorimeter Upgrade Meeting
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Comparison ASIC vs Discrete Solution
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Discrete solution should use Op. Amp. (not at transistor level)
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Room and reliability
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Whatever the solution, power consumption should not be an issue
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Room is an issue (GBT+optical links)
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6U (height) x 30% of the width is allocated to the analog part
Composent could possibly be soldered on both sides
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Two scenarios
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Clipping
1) We want to have a clipping on the base
 Need an ultra low noise system with an accurate input impedance of the
pre-amplifier
 This would probably imply the design of an ASIC
2) Clipping on the base could be removed
 The noise constraint is not so strict
 The PMT base modification is minor (a line to cut on the base PCB)
 A 50Ω resistor at the FEB input should be enough to adapt the line
 Design :
 Discrete solution : the design could be done “quickly”
 Low noise pre-amp
 Delay line clipping
 Delay line integration
 ASIC solution
 Delay line clipping and delay line integration
 Delay line clipping and integration by switch
 Gaussian type shaping (no clipping but tail to be looked at) and
integration by switch
Thursday 26th March 2009
Calorimeter Upgrade Meeting
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FPGA : AX or PA3 ? (I)
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Two problems have been observed with the APA FPGA
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It seems that we need to perform our own tests in order to find and be
persuaded of the “good” solution. Two ways of testing the FPGA have been
thought of :
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When two many bits flip altogether and quickly, the signals seen after the input
buffers of the FPGA are corrupted. This is hardly documented by the
manufacturers and the acceptable limits (number of bits flipping, average rate)
depend on the implementation.
When sending several bits on the FPGA inputs, the internal sampling of the
signals by a unique external clock (and in spite of the usage of a dedicated clock
tree) seems to be done with phase shifted clocks among the registers. This
makes « synchronized » sampling of fast signals more difficult.
Having a prototype dedicated specifically to that problem,
Using the FE-prototype to test the FPGA capabilities.
It appeared that the second way is not favoured as it would increase the
complexity of the design of the FE-prototype both in term of PCB and
firmware.
Wednesday 20th February
Calorimeter : Commissioning Meeting
FPGA : AX or PA3 ? (I)
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Hence, we think that two prototypes have to be made.
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A first prototype to study the performances of the components.
The second prototype would integrate a digital readout of the analog signals and
be the FE-prototype.
This means that the latter would be delayed in time as the first conclusions
on the former need to be obtained.
ProAsic3 seems to be easier to use (reprogrammable) and would be the
baseline. Still, we may imagine that it cannot cope the signals exchanged.
The AX would be the backup solution. But, we also have to prove that the
AX may work.
On the present front-end board we benefited a lot from the Silicon Explorer
to debug the firmware. This does not exist on the APA. It seems that
something similar exists on the ProAsic3. The following questions were
raised :
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Price of the system
Resources needed to make it work
Wednesday 20th February
Calorimeter : Commissioning Meeting
First Prototype (I)
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The first prototype would include
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A ProAsic3
A socket to receive an AX
The possibility to exchange data
 Between the AX and the APA
 From an FPGA to itself
A SPECS mezzanine connector
A digital readout connector : the possibility to perform a readout of the digital
implementation was thought of at this level. We imagined to have a connector
on our prototype and be able to connect a mezzanine having the analog part up
to after the ADC (Barcelona). This would help in checking that the readout may
be performed with the FPGA chosen and may help in having an early and simple
readout for Barcelona.
The GBT standard is not well adapted to the FPGA outputs. We have to design a
system to make the FPGA and GBT compatible. This system should be tested on
this first prototype. If the FPGA-GBT link is mono-polar, a simple tension divisor
was imagined but this would increase the overall consumption (back of the
envelop calculation ~ 1A/80 outputs). The problem is more acute if we want to
have differential outputs (and use the high speed capabilities of the GBT).
NB : the FPGA bit flip problem was linked to the I/O current.
Wednesday 20th February
Calorimeter : Commissioning Meeting
First Prototype (I) – Second Prototype
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We probably have to plan an interface with the analog mezzanine if this
capability is confirmed : clock, SPECS, etc... ?
Two reception areas for two delay chips. Only one would be connected at a time
but we would have the possibility to solder either a Delay25 (CERN) or a LAL
delay chip.
This board would be used « on the table », powered with test bench power
supplies.
The difficulties experienced with the i2c and FPGAs lead to the test of the
transactions with the FPGA on the prototype already.
The possibility to use the first prototype for irradiation tests was mentioned. But
the conditions and purpose of those tests have to be defined precisely.
The second Prototype would use :
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The components tested with the first one
No component testing with this board
The futur trigger implementation was supposed to be identical to the present
one. This has to be confirmed but seemed clear to us. The question of
integrating it to the second prototype was raised.
Wednesday 20th February
Calorimeter : Commissioning Meeting
First Prototype
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Schematic of the first prototype
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Calorimeter Upgrade Meeting
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Tasks and Schedule
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We plan to have a new meeting on April 8th and 9th at Orsay
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Some questions should be answered
 Noise issue should be more understood in case of clipping
 What is the effect of the cables
 Gaussian shaping will be looked at (no clipping but tail ?)
 Pedestal in a switch system
 SPD experience
 Pedestal after AC coupling
 Offset trimming to recover the dynamics
First study of a discrete solution
Usage of the latest software versions to compile the present firmware
Usage of the present firmware on the possible targets (AX, ProAsic3)
Rough idea of the needed resources (I/O, PLL, RAM, banks, ...)
Schematics of the first PCB prototype by June
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PCB by the end of the Summer ?
Thursday 26th March 2009
Calorimeter Upgrade Meeting
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