Transcript FE_ASIC_for_SLHCb_Dec10 - Indico

Analog FE ASIC
Summary and next steps
E. Picatoste, A. Sanuy, D. Gascón
Universitat de Barcelona
Institut de Ciències del Cosmos ICC-UB
Calorimeter upgrade meeting – CERN – June 22th 2010
Outlook
I.
Introduction
II.
Test of the first prototype
III. “Upgrade” of existing blocks
IV.
New blocks
V.
Status and plans
I. Introduction: requirements

Results of the first prototype are compatible with requirements
 With the possible exception is timing
 Allowed jitter for 1 % variation is 3ns instead of 4ns
Value
Energy range
Calibration
Dynamic range
Noise
0-10 GeV/c (ECAL)
Transverse energy
4 fC /2.5 MeV / ADC cnt
Comments
1-3 Kphe / GeV
Total energy
12 fC / ADC count if no clipping
4096-256=3840 cnts :12 bit
<1 ADC cnt or ENC < 5 -6 fC
With clipping in PM base
Termination
50 ± 5 
Passive vs. active
AC coupling
Needed
Low freq. (pick-up) noise
Dynamic pedestal subtraction
(also needed for LF pick-up)
How to compute baseline?
Number of samples needed?
4-5 mA over 25 
50 pC in charge (before clipping)
Clipping
Residue level: 2 % ± 1 % ?
<< ADC cnt
Relevant after clipping?
Baseline shift
Prevention
Max. peak current
Spill-over correction
Spill-over noise
Linearity
< 1%
Crosstalk
< 0.5 %
Timing
Individual (per channel)
Variation < 1% for +/- 2 ns
PMT dependent
Jitter: signal vs. clock



II. Test of the first prototype ICECAL: to be done
Vcc
Ib2
MP2
MP1
1
:
On the input part of the channel
K
MP4
MP3
:
mK
:
mK
∫
Io
Q1
I
 First results shown in the previous talk
Rf
TH
I
Drv
Re
 No major problem found
for the moment
Ii
 Statistic to be completed
Ib1
MN1
 Input impedance and linearity
MN2
Vee
 Residual amplification in reset to be tested
∫
Current amplifier
(mirrors)
First Prototype
 Inductive behaviour of the input impedance to be studied
 Test set-up must be automated for dynamic measurements
on input impedance and linearity
 Cross check of calibrations performed so far
Analog mezzanine with first prototype?
 No track and hold
 Still, we may learn interesting things
Test with spare PM base and cables
 Check noise and signal response
 The sooner we test the final scenario the better
TH
ADC
driver
Analogue
Multiplexer
II. Test of the first prototype: to be done

Test individual blocks
 Characterize as function of bias curremt

Input current amplifier
 Additional statistics on impedance matching
 Study the dynamic range on the current amplifier only
 Very important to think on a connection to an unclipped PM signal

Fully differential OpAmp of the integrator
 In unity gain configuration
 Interesting test to compare with simulation performances:
 GBW
 PM
 Slew Rate
 Overshoot
 Output impedance
 Important to learn if we can use it as output driver for the ADC
II. Test of the first prototype ICECAL: residual amplification in reset

Impact of the residual amplification in reset to be tested
 Additional switches ?
 Not needed according simulations (few % error in the tail)
?
In+
+
+
In-
OutOut+
II. Test of the first prototype ICECAL: inductive behaviour of Zin

We already knew that ICECAL Zin is
slightly inductive at high frequency
|Zin|
 HF is “more reflected” than LF
 Similar to pulse differentiation
However the effect is a bit larger
than expected
Gain+
 Though no problematic (<<1% in area,
Gain-
after integration)
Simulation
Test
VPM
Input signal with reflections
0,01
0,00
0,0E+00
-0,01
VoD2
5,0E-08
1,0E-07
1,5E-07
2,0E-07
2,5E-07
3,0E-07
-0,02
VoD1
-0,03
Icable
(clipped)
[V]

Zin
phase
-0,04
-0,05
IPM
-0,06
Input signal (source)
Input signal (ICECAL)
-0,07
Vi
-0,08
[s]
II. Test of the first prototype ICECAL: inductive behaviour of Zin


The chip has been simulated with (overestimated) bonding inductances
However PCB inductancies have not been considered
 Traces
 Components: AC capacitor must be quite large to average baseline fluctuations
 A typical smd 100 nF capacitor has a resonant frequency of 20 MHz
 An increase in Zin of few ohm at the higher band of the signal is likely
 Use network analyzer to characterize the PCB (S-parameters)
Typical impedance
of a SMD
capacitor
II. Test of the first prototype ICECAL: test set-up

So far, two main problems with the test
 Low degree of automation, maybe ok for 12 chips but…
 Many calibrations have be performed to obtain accurate results
 Timing problems in AWG
 Vertical scale problems in the scope and the differential probe
 We have a nice 1.7 GHz and 20 GS/s DPO scope, but is it really optimal for
this kind of measurements?
 Scope ADC is 8 bits, so many scales are needed…

For signal generation:
 AWG fixed: amplitude and waveform
 Use calibrated attenuator
 Wideband (0-4 GHz)
 Up to 110 dB attenuation
 Programmable
 Used to test other 12 bit measurement systems (Saclay, LPNHE)
 Already bought
II. Test of the first prototype ICECAL: test set-up

For digitization, two different problems
 Acquire the output signal, integrated and (future) sampled
 Acquire the input signal to study input impedance and calibrate gain

Output signal:
 Natural evolution is to use the common board with a 40 MHz ADC
 Build a mezzanine already now?
 Still, if we want to look at signal details (e.g. residual amplification) a higher
sampling rate might be useful
 This the case for input signal, so same solution should be ok

Input signal:
 Alternative method to classical DPO scopes could be high speed analogue memories
 LAL/Saclay family (MATACQ, SAM) is preferred
 12 bit with << 1 % linearity error
 500 MHz and up to 3 GS/s
 Commercial products exist (CAEN - V1729A and Wavecatcher-USB?)
 Only problem is that standard is 50 Ohm connection
 Contact D. Breton / E. Delagnes to see how to adapt (and what)
III. Upgrade of existing blocks: preamplifier

So far, basic performance of the preamplifier seems to be ok

However, to go to the final design we need to answer two
questions?
 Will we control electronically the input impedance ?
 Do we want that the chip is able to accept an unclipped signal ?

Control of the input impedance:
 To compensate possible process variations
 Use a resistor in parallel (or series) to the input impedance
 In case of large waver to wafer or die to die fluctuations it can be painful
 Accurate chip selection and grouping
 Drifts???
 Modify the input amplifier so we can control the input impedance electronically
III. Upgrade of existing blocks: preamplifier

Input impedance controllable:
 Tune second feedback current
Vcc
1
 Binary weighted ladder (3 bits?):
K
:
mK
:
Current
ladder
Rf
Re
Ii
Ib1
MN1
 Fix the value per ASIC, set by:
MN2
Vee
 External jumper
 Slow control: dig interface required
 Automatic tunning
mK
Q1
 Let’s design and simulate …
How control current ladder control?
:
MP4
MP3
Io
 A priori looks like reasonable

MP2
MP1
Ib2
Vcc
Rext
 Reference voltage
 Reference currents: external or band gap
 External resistor
 Wilkinson or SAR ADC style logic
+
Rint
Current
ladder
Iref
Iref
n
Logic
n
III. Upgrade of existing blocks: preamplifier

Accept an unclipped signal is a “safety requirement”, in case:
 Large pick-up noise coupled after the clipping
 Additional reduction of PM HV is eventually needed

The impact on the ICECAL design is two-fold:
 The gain must be tuneable
 Mostly covered by the integrator, see next slides
 The signal range must be high enough
 Key issue is the current mode preamplifier

Without clipping:
 The signal charge is approximately 3 times larger
 Total PM delivered charge (50pC) would be sensed
 The input peak current is approximately 2 times larger
 Maximum input peak current of about 3 mA
III. Upgrade of existing blocks: preamplifier
According to simulations signal range is about 2 mA peak (3.3 V)
 To be tested
Gain+
Gain-
 Study how to optimize this parameter
 Increase supply voltage (3.5 V possible)
 Switch between two mirror configurations
~ 1.5 Ω
|Zi|

Worst case: Z i 
Vi , peak
I i , peak
III. Upgrade of existing blocks: integrator

Tuneable resistor RF in parallel with feedback capacitor CF
 To increase integrator output “flatness” around sampling point
 As an alternative to clipping (RF CF about 20 ns)

Tuneable feedback capacitor CF ?
 Standard operation (clipping at PM base): 7 pF
 No clipping: about 15 pF
 Input charge is about 3 times larger
 However, RF introduce leakage
 Maybe it would be better to decrease preamp gain…
CF
In+
RF
+
+
In-
RF
CF
OutOut+
IV. New blocks

Prototyped in June AMS run:

To be tested in future runs:
Low noise current amplifier:




Basic schemes
Integrator:


High GBW fully differential OpAmp
 Could be used in other stages


Compensation of process variation
of amplifier’s input impedance
Track and hold (if needed)
Analogue multiplexer
ADC driver
ADC needs to be characterized
Common blocks:
 Clock generation
 Biasing (CMOS band gap already exists)


∫
I
TH
I
Drv
∫
Current amplifier
(mirrors)
TH
ADC
driver
Analogue
Multiplexer
V. Status and plans

This prototype was intended as “a proof o principle”:
 Seems to be ok
 Still a lot of test to be done

Lots of things to design
 Modify current blocks to add tuneability
 Input impedance, control of integrator shape and gain
 New blocks to be designed:
 T&H and Multiplexer are the most critical
 Flip around scheme ?
 Bias and slow control
V. Status and plans

Plans for 2011
 Test and design until Q3 2011
 There is no clear need of making more “partial” prototypes
 Iterations are time consuming
 Go for a complete channel implementation
 Submit a prototype with few complete channels in Q4 2011
 Still possible to send a critical block in June 2011 if needed
 Goal of submitting a complete channel in Q4 2011 should be preserved

And for 2012, if everything is ok…
 Test beam ?
 Radiation tests?
BACK-UP
Issues related to common aspects of LHCb electronic upgrade

DC-DC converter vs linear regulators
 DC-DC is the baseline, however …

Synchronous reset to synchronize subchannel to BID
 In principle should be there
Possible alternative to delay line clipping or gaussian shaping
Jacques’ idea
Cf (1 pF)
Rfi
Rgi (1 K)
+
Vi
Possible alternative to delay line clipping or gaussian shaping
Possible alternative to delay line clipping or gaussian shaping