Transcript Update on SP02 Design, corrected

Update on
SP02 design
by Victor Golovtsov & Lev Uvarov
Trigger Meeting at Rice
August 2002
Outline
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Design Status
GTLP Backplane Termination
FPGA Configuration
Boundary Scan
Aug 22, 2002.
2
Victor Golovtsov,
Lev Uvarov
PNPI / University of Florida
GTLP Backplane Termination
Rephrasing the
“Recommendation on GTLP bus Implementation”:
As
shown in fig below, Vref is set by an R/2R resistor network
between VTT and GND.
The resistor network maintains balanced upper and lower noise
margins for any termination voltage fluctuations.
So
Vref
should be generated locally on each card
Since the termination network and VTT resides on the backplane,
the card resistor network should take VTT from the BACKPLANE
through a CCB connector pin.
SP02 design expects VTT to be available through B11 pin.
Design Status
Aug 22, 2002.
3
Victor Golovtsov,
Lev Uvarov
PNPI / University of Florida
FPGA Configuration Modes
SP02 carries 7 Virtex-II FPGAs on the main board plus
1 Virtex-II FPGA on the Mezzanine Card.
Configuration Modes (selected by switchers)
Design Status
FPGA
Boundary
Scan
Master
Serial
Front
Yes
Yes
VME/CCB
Yes
Yes
DDU
Yes
Yes
Main (SP)
Yes
Aug 22, 2002.
Master
SelectMAP
Yes
4
Victor Golovtsov,
Lev Uvarov
PNPI / University of Florida
Boundary Scan
Two tasks for boundary scan interface:
 Testing
the JTAG-compatible hardware for shorts and opens per IEEE 1149.1
(All Xilinx devices plus all GSI SRAMs, 65 devices total)
 Configuring
FPGAs per IEEE 1532 (All Xilinx device, 20 devices total)
Three options to port to a local JTAG chain (chains):
 Header
for Xilinx’ Parallel Cable IV (2 mm pitch)
 National
SCANSTA111 Enhanced SCAN Bridge (one per SP02, supports up to
3 local chains). Uses the VME64x T&Mbus, but requires Boundary Scan
Master in a Crate.
 National
SCANSTA101 Boundary SCAN Master (one per SP02, supports just
one local chain). Requires a fuse-based CPLD for an auxiliary VME interface
in each SP02.
Third approach (with older 5V devices) has been successfully implemented in the
first SP prototype.
Second approach has been implemented and tested by Nuno Vaz Cardoso and
Jose Carlos Da Silva from HC group.
Design Status
Aug 22, 2002.
5
Victor Golovtsov,
Lev Uvarov
PNPI / University of Florida
Boundary Scan - continue
They ported the SCAN Master functionality in the HDL form in the
CPLD, built the VME card, as well as several test cards that used
SCANSTA111 devices.
They also built a GUI (wrapper) around National’s ScanEase
software.
The software used by both approaches is just the same. It is
National’s command line utility ScanEase (Rev.2.0). Building a
wrapper is a user’s problem.
Needs to be mentioned here that both SCANSTA101 and
SCANSTA111 are available either in silicon or in the HDL form.
In the HDL form, each occupies about 15K gates.
So, a big enough CPLD would carry both VME interface and
SCANSTA functionality.
Alex M. already got in touch with Ken Filliter from National, who
provides support for SCAN devices and SCANEASE software.
Design Status
Aug 22, 2002.
6
Victor Golovtsov,
Lev Uvarov
PNPI / University of Florida
Boundary Scan - continue
Second approach has been implemented already in
SP02 design, counting on already existed Boundary
Scan Controller design at CERN. ( they schedule to
launch production of their board this fall, so they
could have ordered extra boards).
But this may change if the third option finally prevails.
In this case the JTAG interface will be redone.
Design Status
Aug 22, 2002.
7
Victor Golovtsov,
Lev Uvarov
PNPI / University of Florida
Mezzanine Card
Mezzanine card interfaces, as well as its dimensions
are fully determined
6 Samtec FOLC/MOLC connectors carry 780 signals,
16 power and 84 ground pins.
The card can accept either XC2V4000 or XC2V6000
devices.
It is designed with auxiliary power and JTAG
connectors to facilitate testing.
The card image can be found on the “SP02 layout”
slide.
Design Status
Aug 22, 2002.
8
Victor Golovtsov,
Lev Uvarov
PNPI / University of Florida
SP02 Layout slide shows current status of the board.
What’s new:
Two
stiffeners from both sides of Front FPGAs
Switchers
added, one per Xilinx device, for debugging
purpose.
Backplane
connectors moved a little bit, to be closer to
corresponding drivers/receivers
DDU
FPGA jumped to the next package size (from fg256 to
fg456)
Number
JTAG
of buffers added to segment long traces
port implementation seems to be the only unresolved
issue.
Design Status
Aug 22, 2002.
9
Victor Golovtsov,
Lev Uvarov
PNPI / University of Florida
SP02 Board Layout
DC-DC Converter
Phi Global LUT
Eta Global LUT
Phi Local LUT
EEPROM
Stiffener
Indicators
VME/CCB
FPGA
FM RJ45
TLK2501
Transceiver
From CCB
Front FPGA
To MS
DDU FPGA
PT LUT
Main
FPGA
Mezzanine
Card
Optical
Transceiver
Design Status
Aug 22, 2002.
10
Victor Golovtsov,
Lev Uvarov
MB1-to-SP
ME1-to-DT
PNPI / University of Florida