Transcript Final Presentation

Presented by:
Reshef Schreiber
Itay Leibovitz
Instructed by:
Eran Segev
Board Objectives

The second part of the Serial Communication Board
(SCB) project adds USB Host capability to the SCB
mezzanine board designed in part I and by that
expanding its I/O capabilities

The SCB interfaces mechanically and electrically to
the External Memory Interface (EMIF) connectors of
the evaluation board

To evaluate the use of the Philips ISP1362 USB
controller
DSP Evaluation Board
SCB Interface
Power
3.3 V
Power
5V
External Memory
Interface (EMIF)
Interrupts
SCB
USB
EMIF

The memory signals required for the daughtercard interface connectors are:

Address pins


Data pins


16 data signals are provided to facilitate access to
memory and parallel peripherals.
Chip Select


7 address signals of the DSP are provided to give the
address space to the daughter-card.
CE3 is provided to access individual memory and I/O
space.
Byte Enable

BE0, BE1 are used in order to access the 16 bit words
out of the 32bit wide words of the DSP.
SCB Block Diagram
D(0:15)
RD
WR
ADR(1:0)
INT1
BE0,BE1
ADR(6:0)
CS
FPGA
CS
ISP1362
SCB Main Blocks

Address Decoder: used to bridge between the DSP
EMIF and the USB host controller. The FPGA decodes
the control signals of the EMIF bus to a simple control
line (CS) needed by the USB controller.

USB Host Controller: The USB host functions are
controlled using various control registers and status
ports. These I/O ports (read and write) are accessed by
the DSP using a special “two phase” access.
FPGA Main Function
BE0,BE1
ADR(6:0)
CS
ADDRESS
DECODER
CS
FPGA Signal Description
Signal Name
Direction
Description
ADDRESS(8:2)
I
Address bus. Defines the unit to be accessed
CE3#
I
Memory space enables. When low indicates
access to the EMIF space of the SCB.
BE(1:0)#
I
Byte enables. When low indicates that the data is
present on the low byte.
AOE#
I
Asynchronous output enables.
CS
O
chip select output (active LOW); enables the HC
driver to access the buffer memory and registers
of the HC.
CLK
I
Altera clock input.
Address Decoding (1)




The ISP1362 is made of a Host Controller (HC) and a Device Controller
(DC)
The ISP1362 Chip Select (CS) is shared between the HC and the DC
Each Controller has two I/O ports :
 Command port
 Data port
Access to each of these ports is made by a combination of the following
control signals:
 A0,A1,CS
CS A1
A0
ACCESS Width(bits)
description
0
0
0
R/W
16
HC data port
0
0
1
W
16
HC command port
0
1
0
R/W
16
DC data port
0
1
1
W
16
DC command port
Address Decoding (2)


The right combination of control signals that will force the CS to Low is:
Address
BE1
BE0
CE3
00000XX
0
0
0
The absolute addresses of the relevant ports (in the DSP memory space) are defined
using the CE programming in the DSP initialization
Address
R/W
Device Selected
0xA0000000
R/W
HC data port
0xA0000002
W
HC command port
0xA0000004
R/W
DC data port
0xA0000006
W
DC command port
ISP1362
ISP1362 Description

The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go
(OTG) controller integrated with the advanced Philips Slave Host
Controller (PSHC) and the Philips ISP1181B Device Controller (DC).

Only the Host Controller is implemented in the SCB.

The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be
hardware configured to function as a downstream port, an upstream
port or an OTG port, Whereas port 2 can only be used as a
downstream port. The SCB uses only the HC port which is port 2.

attributes:



Supports integrated physical 4096 bytes of multi-configuration memory
Supports all four types of USB transfers: control, bulk, interrupt and
isochronous
Directly addressable memory architecture; memory can be updated onthe-fly
ISP1362 Signal Description
Signal Name
Direction
Description
A0
I
When pulled low, choose data phase. When pulled high
choose command phase.
A1
I
When pulled low, choose HC port. When pulled high
choose DC port.
I/O
Data bus. Connects to the low word of the evaluation
board.
DATA(15:0)
CS
I
chip select input (active LOW); enables the HC driver to
access the buffer memory and registers of the HC.
INT1
O
Interrupt request from the HC; provides a mechanism for
he HC to interrupt the microprocessor.
X1
I
Crystal input. This pin is connected to an external clock
oscillator, leave the X2 pin open.
X2
O
Crystal output. Left open, because X1 is connected to an
external clock oscillator.
H_DP2
I/O
Downstream D+ signal; host only, port 2. Connects to D+
pin in the USB connector. Has internal pull up resistor.
H_DM2
I/O
Downstream D- signal; host only, port 2. Connects to D+
pin in the USB connector. Has internal pull up resistor.
PIO interface of the ISP1362
PIO Register Access

The ISP1362 has 2 types of registers:
 16 bit registers
 32 bit registers.

The 16 bit registers access is made in 2 stages:
 Command stage.
 Data stage.

The first stage (command stage) chooses the register address. It is done by
simply writing the register’s address to the command port of the HC.
Before continuing to the next stage, CS must be kept inactive (high) for at
least 300 ns.
The second (data) stage enables reading/writing to the port defined in the in
the command stage.
The 32 bit registers access is made in 3 stages: one command stage and two
data stages.



Reading 16/32 bits register
Writing 16/32 bits register
Software Objectives

The software developed includes the driver for the
SCB which provides the card with the basic ability
to function as a general USB host. Specific
implementations will make use of these functions to
build a dedicated driver.

The driver runs on the DSP and serves as the HCD
(Host Controller Driver) of the ISP1362.
Software Implementation
The software consists of 3 main layers:



Main program takes care of initialization of the
SCB and the ISP1362.
Functions for reading and writing to the ISP1362’s
registers and buffer. These are later used for
configuring the ISP1362.
Functions for arranging USB transfers from the
attached device.
The Main Program
Checking Existence of
Host Controller
 Writing a specific value into a scratch
register and reading it.
A Software Reset is issued by the HCD.
Software Reset
The buffer memory of the HC is
shared by the isochronous, interrupt
and control functions.
Initiate buffer sizes
Several characterizations of the HC
are set by evaluating the ISP1362’s
registers.
Hardware Configuration
The HC is generating SOF packets
and is ready to operate.
Device
Connected ?
Enumeration
Operational
Mode
Interrupts

The ISP1362 HC generates interrupts on
several events:



Unrecoverable Error
Frame Number Overflow
Device Connection
Philips Transfer Descriptor (PTD)

A PTD is a struct that consists of a PTD header and a payload
data.

The PTD provides a communication channel between the
HCD and the ISP1362 USB HC.

A PTD header contains information required for data transfer,
such as data packet size, transfer status and transfer token
types.

Certain fields in the PTD header are used by the HC to inform
the HCD about the status of the transfer.
PTD Header
Settings:

Speed





Maximum Packet Size
Endpoint Number
Total Bytes
Token Type


Low Speed/High Speed
IN/OUT/SETUP
Address
PTD Header
Status:



Actual Bytes transferred
Active – transfer
completed
Completion Code

Success/Failure
Enumeration

When a USB device is attached to or removed
from the ISP1362, the host uses a process
known as bus enumeration to identify and
manage the device state changes necessary.

Several functions were written in order to take
care of the enumeration process of the device.
Auxiliary Functions

make_control_ptd
 Constructs the PTD given the relevant parameters passed to it
and a pointer.

Send_Control
 this function sends out the packet to the device.
 polls Active Bit to determine when the transaction is completed.
 stores the reply in a dedicated buffer.

Set_Address
 assigns a unique address by sending a Set Address request in a
containing the new address.
Control

The function Get_control is used for getting the Descriptors from the
device upon connection.
 Device Descriptor
 A device descriptor describes general information about a USB
device.

Configuration Descriptor
 A configuration descriptor describes information about a specific
device configuration. all related interface and endpoint descriptors
are returned.

Set Configuration
 The device is set to its default configuration.

The device is now enumerated and ready for
data transactions.

For testing, The HCD contains functions for
generating a Bulk compatible PTD, and for
sending and receiving bulk data transactions.