Transcript Slide 2 CMOS VLSI Design

CMOS VLSI
Design
CMOS Transistor Theory
Outline







Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models
CMOS VLSI Design
Slide 2
Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed
 Also explore what a “degraded level” really means
CMOS VLSI Design
Slide 3
MOS Capacitor
 Gate and body form MOS capacitor
 Operating modes
– Accumulation
– Depletion
– Inversion
Vg < 0
+
-
(a)
polysilicon gate
silicon dioxide insulator
p-type body
Accumulation
0 < V g < Vt
+
-
depletion region
Depletion
(b)
V g > Vt
+
-
inversion region
depletion region
Inversion
(c)
CMOS VLSI Design
Slide 4
Terminal Voltages
Vg
 Mode of operation depends on Vg, Vd, Vs
+
+
– Vgs = Vg – Vs
Vgs
Vgd
– Vgd = Vg – Vd
Vs
Vd
– Vds = Vd – Vs = Vgs - Vgd
+
Vds
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation
CMOS VLSI Design
Slide 5
nMOS Cutoff
 No channel
 Ids = 0
 No channel formed
until Vgs > Vt
Vgs = 0
+
-
g
+
-
s
d
n+
n+
Vgd
p-type body
b
CMOS VLSI Design
Slide 6
nMOS Linear
 Channel forms
 Current flows from d to s
V
– e from s to d
 Ids increases with Vds
 Similar to linear resistor
gs
> Vt
+
-
g
+
-
s
d
n+
n+
Vgd = Vgs
Vds = 0
p-type body
b
Vgs > Vt
Vds = Vd – Vs = Vgs - Vgd
+
-
g
s
d
n+
The larger the Vds, the smaller the
Vgd
CMOS VLSI Design
+
n+
Vgs > Vgd > Vt
Ids
0 < Vds < Vgs-Vt
p-type body
b
Slide 7
CMOS VLSI Design
Slide 8
nMOS Saturation
 Channel pinches off, when Vgd < Vt, no surface
inversion near the drain.
 Ids independent of Vds
 We say current saturates
 Similar to current source
Vds = Vd – Vs = Vgs – Vgd
Saturation occurs when
Vds > Vgs – Vt
Vsat = Vgs – Vt
Vds > Vsat
CMOS VLSI Design
Vgs > Vt
+
-
g
+
-
Vgd < Vt
d Ids
s
n+
n+
Vds > Vgs-Vt
p-type body
b
Slide 9
I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
CMOS VLSI Design
Slide 10
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel =
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
CMOS VLSI Design
Slide 11
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel = CV
 C=
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
CMOS VLSI Design
Slide 12
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
Cox = ox / tox
 Qchannel = CV
capacitance per unit
 C = Cg = oxWL/tox = CoxWL
area
 V=
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
CMOS VLSI Design
Slide 13
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel Vc = ½(Vs+ Vd) = Vs- ½(Vs) + ½(Vd)
Vgc= Vg-Vc = Vg- Vs – ½(Vds)
 Qchannel = CV
Cox = ox / tox
 C = Cg = oxWL/tox = CoxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt Vt used to create inversion layer
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
CMOS VLSI Design
Slide 14
Carrier velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v=
CMOS VLSI Design
Slide 15
Carrier velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE
m called mobility
 E=
CMOS VLSI Design
Slide 16
Carrier velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE
m called mobility
 E = Vds/L
 Time for carrier to cross channel:
– t=
CMOS VLSI Design
Slide 17
Carrier velocity
 Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
 v = mE
m called mobility
 E = Vds/L
 Time for carrier to cross channel:
– t=L/v
CMOS VLSI Design
Slide 18
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
I ds 
CMOS VLSI Design
Slide 19
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t

CMOS VLSI Design
Slide 20
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
W
 mCox
L
Q = CV, t = L/v
V  V  Vds
 gs t
2

V
  Vgs  Vt  ds Vds
2

CMOS VLSI Design
V
 ds

W
 = mCox
L
Slide 21
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
I ds 
CMOS VLSI Design
Slide 22
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now increasing drain voltage no longer increases
current
V
I ds   Vgs  Vt  dsat Vdsat
2

CMOS VLSI Design
Slide 23
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now increasing drain voltage no longer increases
current
Vdsat

I ds   Vgs  Vt 
2



V

2
CMOS VLSI Design
gs
 Vt 
V
 dsat

2
Slide 24
nMOS I-V Summary
 Shockley 1st order transistor models


0

 
Vds
I ds    Vgs  Vt 
2


2


Vgs  Vt 


2
CMOS VLSI Design
Vgs  Vt
V V  V
 ds
ds
dsat

Vds  Vdsat
cutoff
linear
saturation
Slide 25
Example
Vgs = 5
Vgs = 4
Ids (mA)
 Assuming using a 0.6 mm process
– From AMI Semiconductor
– tox = 100 Å
2.5
– m = 350 cm2/V*s
2
– Vt = 0.7 V
1.5
 Plot Ids vs. Vds
1
– Vgs = 0, 1, 2, 3, 4, 5
0.5
– Use W/L = 4/2 l
0
0
 3.9  8.85  1014   W 
W
W
  mCox   350 

120
m A /V 2
 

8
L
L
 100  10
 L 
CMOS VLSI Design
Vgs = 3
Vgs = 2
Vgs = 1
1
2
3
4
5
Vds
Slide 26
pMOS I-V
 All dopings and voltages are inverted for pMOS
 Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V*s in AMI 0.6 mm process
 Thus pMOS must be wider to provide same current
– In this class, assume mn / mp = 2
CMOS VLSI Design
Slide 27
Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion
CMOS VLSI Design
Slide 28
Gate Capacitance
 Approximate channel as connected to source
 Cgs = oxWL/tox = CoxWL = CpermicronW; where
Cpermicron = CoxL = ox/tox L
 Cpermicron is typically about 2 fF/mm
polysilicon
gate
W
tox
L
n+
n+
SiO2 gate oxide
(good insulator, ox = 3.90)
p-type body
CMOS VLSI Design
Slide 29
Diffusion Capacitance
 Csb, Cdb due to reverse biased p-n junction between
source and body; between drain and body.
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
– Make diff area small
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process
Continue Section 2.3, 2.4, on white board
CMOS VLSI Design
contacted diff
uncontacted diff
Slide 30