Transcript lecture4 - Clarkson University

EE365
Adv. Digital Circuit Design
Clarkson University
Lecture #4
Transistor Level Logic
CMOS vs. TTL
Topics
• CMOS Logic Devices
• Bipolar Logic Devices
Lect #4
Rissacher EE365
MOS Transistors
Voltage-controlled resistance
PMOS
NMOS
Lect #4
Rissacher EE365
Switch Model
Lect #4
Rissacher EE365
CMOS Inverter
Lect #4
Rissacher EE365
Alternate transistor symbols
Lect #4
Rissacher EE365
CMOS Gate Characteristics
• No DC current flow into MOS gate terminal
– However gate has capacitance ==> current required for
switching (CV2f power)
• No current in output structure,
except during switching
– Both transistors partially on
– Power consumption related
to frequency
– Slow input-signal rise times
==> more power
• Symmetric output structure
==> equally strong drive in
LOW and HIGH states
Lect #4
Rissacher EE365
CMOS Gate Operation
• Java applet showing CMOS gates
– visit:
tech-www.informatik.unihamburg.de/applets/cmos/
– illustrates gate operation, including power drain
during switching
– Link is on class website
Lect #4
Rissacher EE365
Pull-up / Pull-down Model
• Typical CMOS gate can be viewed as
consisting of two parts
– pull-up network and pull-down network
VDD
A
B
C
Pull-up
output
A
B
C
Pulldown
GND
Lect #4
Rissacher EE365
Pull-up / Pull-down Model
• High level inputs to the PDN cause
switches to close
• If there is a closed switch path thru
PDN, then output is low
• Low level inputs to the PUN cause
switches to close
• If there is a closed switch path thru
PUN, then output is high
Lect #4
Rissacher EE365
Pull-up / Pull-down Model
A
A and ( B or C)
B
C
Since hign level signals on
the inputs cause the PDN to
close switches, we get a
Boolean expression for the
input which creates a closed
path thru PDN
If a closed path exists in PDN, then the output is pulled low.
Thus the logic function realized is the complement (inverted)
version of the Boolean expression.
output
A
B
C
Pulldown
not (A and ( B or C))
GND
Lect #4
Rissacher EE365
Pull-up / Pull-down Model
What happens when the Boolean expression is false?
V dd
Since there is no path thru PDN, the output could float.
In order to make the output high, the PUN must have a path which
connects VDD to the output.
Observe: take the expression for PDN and use DeMorgans Law to write
it in terms of complemented input variables. Complemented variables
are true when the input level is low. Thus, this gives exactly the form of
the PUN
B
A
C
In this case: not A or ( not B and not C)
Lect #4
Rissacher EE365
CMOS NAND Gates
• Use 2n transistors for n-input gate
Lect #4
Rissacher EE365
CMOS NAND -- switch model
Lect #4
Rissacher EE365
CMOS NAND -- more inputs
(3)
Lect #4
Rissacher EE365
CMOS – non-inverting buffer
Lect #4
Rissacher EE365
CMOS – 2-input AND gate
• Note the number of transistors compared to NAND (6
vs. 4)
Lect #4
Rissacher EE365
In-Class Practice Problem
• Design a CMOS NOR circuit
• Hint: Like NAND shown earlier, NOR
circuits have 2n transistors for n-input
gate (this one has 4)
Lect #4
Rissacher EE365
CMOS NOR Gates
• Like NAND -- 2n transistors for n-input
gate
Lect #4
Rissacher EE365
NAND vs. NOR
• NMOS has lower “on” resistance than PMOS
(important when multiple transistors are in series)
NAND
NOR
• Result: NAND gates are preferred in CMOS due to
speed
Lect #4
Rissacher EE365
Cascade Structure
for Large Inputs
• 8-input CMOS NAND
Lect #4
Rissacher EE365
Complex Logic Functions
• CMOS AND-ORINVERT gate
Lect #4
Rissacher EE365
Tri-State
• We lied “binary” outputs have more than two values
• Some gates are designed to have a
third value - a high impedance
• Effectively disconnects the gate output
from the circuit
Lect #4
Rissacher EE365
Tri-State Application
En
A
F
En_ A
If EN = 1, then F = A'
if En = 0, then F is open circuited,
denoted Hi-Z
A
B
En_ A * A' + En_A' * B '
Lect #4
Rissacher EE365
Open Drain
• Device without the internal active pullup network on the output
• Why ?
– Allows for two or more outputs to be
connected together
– Produces a “wired” AND function
• Requires a pull-up resistor
Lect #4
Rissacher EE365
Open Drain Application
+5v
A
B
C
D
E
F
Lect #4
(AB)' (CD)' (EF)'
=
[AB + CD + EF] '
Rissacher EE365
CMOS Families
•
•
•
•
•
•
Lect #4
4000 series - mostly obsolete
HC
HCT (input levels compatible with TTL)
AC
ACT (input levels compatible with TTL)
FCT and FCT-T (both TTL compatible)
Rissacher EE365
Bipolar Logic Families
Lect #4
Rissacher EE365
TTL Digital Circuits
• Designed using “transistor-transistor
logic” (remember EE341 ?)
– npn bipolar junction transistors
• Transistors operate in either
– cut-off mode
• no base current => no collector current
– saturated mode
• base current pulls VCE to ~ 0.2 v
Lect #4
Rissacher EE365
A Simplified TTL NAND Gate
+5V
A
B
Vout
Lect #4
Rissacher EE365
Schottky Transistors
• Addition of Schottky diodes between
base and collector prevent saturation
• Schottky diode has lower forward bias
voltage drop (0.25 v).
• Resulting design is called a Schottky
transistor
• Speeds switching time by reducing
charge storage in saturation
Lect #4
Rissacher EE365
TTL NAND Gate
Lect #4
Rissacher EE365
Special TTL outputs
• Standard output stage is called “totem
pole” output
• Tri-state outputs
• Open collector (or CMOS open drain)
– requires external pull-up resistor
– allows wired-AND function
Lect #4
Rissacher EE365
TTL differences from CMOS
• Asymmetric input and output characteristics.
• Inputs source significant current in the LOW
state, leakage current in the HIGH state.
• Output can handle much more current in the
LOW state (saturated transistor).
• Output can source only limited current in the
HIGH state (resistor plus partially-on
transistor).
• TTL has difficulty driving “pure” CMOS inputs
because VOH = 2.4 V (except “T” CMOS).
Lect #4
Rissacher EE365
TTL Families
•
•
•
•
•
•
Lect #4
7400 series (5400 “mil spec”)
74 S - Schottky
74 LS - low power Schottky
74 AS - advanced Schottky
74 ALS - advanced low power Schottky
74 F - Fast TTL
Rissacher EE365
TI’s Logic Products
9/10/98
Lect #4
Rissacher EE365
Comparison of Signal Levels
CMOS
(HC, AC)
CMOS
(HCT, ACT)
5v
VOH
4.4 v
VIH
3.5 v
VIL
VOL
Lect #4
TTL
(S, LS, AL, ALS, F)
5v
5v
VOH
2.4 v
VOH
2.4 v
VIH
2.0 v
VIH
2.0 v
VIL
VOL
0.8 v
0.4 v
0v
VIL
VOL
0.8 v
0.4 v
0v
1.5 v
0.5 v
0v
Rissacher EE365
Another Practice Problem
• Attempt to draw a truth
table for the following
circuit. Hint: List each
transistor in the truth
table and show
whether it is on of off
for each input
combination
Lect #4
A
B
C
D
Rissacher EE365
Another Practice Problem
Z
H
H
H
H
H
L
L
L
H
L
L
L
H
L
L
L
Lect #4
• OR-AND-INVERT
Rissacher EE365
Next Classes
• Memorial Day – NO CLASS !
• Tues. - Help Day for Project #
• Wed. – Class Postponed
• Thur. - Electrical Behavior, Power & Timing