Transcript Document

EE365
Adv. Digital Circuit Design
Clarkson University
Lecture #14
SRAM & DRAM
Topics
• SRAM
• DRAM
Lect #15
Rissacher EE365
Read/Write Memories
• a.k.a. “RAM” (Random Access Memory)
• Volatility
– Most RAMs lose their memory when power is
removed
– NVRAM = RAM + battery
– Or use EEPROM
• SRAM (Static RAM)
– Memory behaves like latches or flip-flops
• DRAM (Dynamic Memory)
– Memory lasts only for a few milliseconds
– Must “refresh” locations by reading or writing
Lect #15
Rissacher EE365
SRAM
Lect #15
Rissacher EE365
SRAM operation
• Individual bits are D latches, not
edge-triggered D flip-flops.
– Fewer transistors per cell.
• Implications for write operations:
– Address must be stable before writing cell.
– Data must be stable before ending a write.
Lect #15
Rissacher EE365
SRAM
array
Lect #15
Rissacher EE365
SRAM
control
lines
• Chip select
• Output enable
• Write enable
Lect #15
Rissacher EE365
SRAM read timing
• Similar to ROM read timing
Lect #15
Rissacher EE365
SRAM write timing
• Address must be stable before and after
write-enable is asserted.
• Data is latched on trailing edge of (WE & CS).
Lect #15
Rissacher EE365
Bidirectional data in and out pins
• Use the same data pins for reads and writes
– Especially common on wide devices
– Makes sense when used with microprocessor
buses (also bidirectional)
Lect #15
Rissacher EE365
SRAM devices
• Similar to ROM packages
Lect #15
28-pin DIPs
32-pin DIPs
Rissacher EE365
Synchronous
SRAMs
• Use latch-type
SRAM cells
internally
• Put registers in
front of address and
control (and maybe
data) for easier
interfacing with
synchronous
systems at high
speeds
• E.g., Pentium
RAMs
Lectcache
#15
Rissacher EE365
DRAM (Dynamic RAMs)
• SRAMs typically use six transistors per
bit of storage.
• DRAMs use only one
transistor per bit:
• 1/0 = capacitor
charged/discharged
Lect #15
Rissacher EE365
DRAM read operations
–
–
–
–
–
Lect #15
Precharge bit line to VDD/2.
Take the word line HIGH.
Detect whether current flows into or out of the cell.
Note: cell contents are destroyed by the read!
Must write the bit value back after reading.
Rissacher EE365
DRAM write operations
– Take the word line HIGH.
– Set the bit line LOW or HIGH to store 0 or 1.
– Take the word line LOW.
– Note: The stored charge for a 1 will eventually leak off.
Lect #15
Rissacher EE365
DRAM charge leakage
• Typical devices require each cell to be
refreshed once every 4 to 64 mS.
• During “suspended” operation, notebook
computers use power mainly for DRAM
refresh.
Lect #15
Rissacher EE365
DRAM-chip internal organization
64K x 1
DRAM
Lect #15
Rissacher EE365
RAS/CAS operation
• Row Address Strobe, Column Address Strobe
– n address bits are provided in two steps using n/2
pins, referenced to the falling edges of RAS_L and
CAS_L
– Traditional method of DRAM operation for 20
years.
– Now being supplanted by synchronous, clocked
interfaces in SDRAM (synchronous DRAM).
Lect #15
Rissacher EE365
DRAM read timing
Lect #15
Rissacher EE365
DRAM refresh timing
Lect #15
Rissacher EE365
DRAM write timing
Lect #15
Rissacher EE365
Next time
• There is no next time
• Next Class: I’ll be here to answer
any exam questions
Lect #15
Rissacher EE365