Transcript Slide 1

Noise Analysis and
Simulation of a Two-Step
Successive
Approximation ADC
B.Sc. Thesis by
Çağrı Gürleyük
040060345
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17.07.2015
Introduction
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Two-step Successive Approximation Register
Analog to Digital Converter Noise Analysis
Noise Analysis of a Switched Track and Hold
Noise Analysis of a Switched Amplifier
Noise Analysis of the SAR ADC
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Motivation of the Thesis
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Develop a method of analysis for a simple circuit
(switched capacitor track and hold) and
correleate it with simulation results.
Develop a method of analysis for a more
complex circuit (switched capacitor amplifier)
and correleate it with simulation results.
Having correleated analysis and simulation;
apply the method to a more complex, hard to
analyze circuit.
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The Successive Approximation ADC
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Nyquist-rate data converter
implementing the binary
search algorithm.
Suitable for mediumresolution, medium-speed
applications.
Uses digital logic to
implement the SAR
algorithm. Uses an analog
sample and hold,
comparator, and DAC.
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Noise Analysis
• Continuous Time Linear Time Invarient Circuits
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Inherently linear (if the opamp is assumed to be so.) SPICE NOISE
analysis runs on linear circuits; thus a perfect match.
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Noise Analysis
• Resistor noise filtered by a capacitor. Integration of noise
yields vn2 = kT/C.
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Noise Analysis
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What about a switched circuit?
• Has two (or more) steady state operating points, which due to
charge transfer between capacitors, have transient effects.
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Simulating Noise in Switched
Capacitor Circuits
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PSS and PNOISE from
SpectreRF
 Transient Noise from Spectre
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Introduces the concept of a
periodic operating point.
(Periodic Steady State) Uses
frequency domain decomposition
to assess the behaviour of the
circuit at its ‘periodic’ operating
point and its harmonics.
• Uses traditional transient
analysis methods, by injecting
noise. Solves nonlinear device
equations, most accurate
device representations
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Higher frequency components
mean increased simulation time.
• Higher noise frequency means
reduced simulation steps, thus
increased simulation time.
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Analyzing the Switched
Capacitor Track and Hold
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The simplest imaginable switched circuit with a periodic operating
point.
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Analyzing the Switched
Capacitor Track and Hold
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Sampling operation results in aliasing.
• Integrated noise
figure:
vn2 = kT/C
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PNOISE
Simulation
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Small-signal analysis over a periodic operating point. Sinc colored
noise spectrum. Integrating yields kT/C.
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Transient Noise
Simulation
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Frequency spectrum is obtained by coherent sampling. Power is
extracted by IQ Modulation. Integrated to yield kT/C.
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Which one to choose? Transient Noise.
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Both noise simulation methodologies were compared; along with the
time required to run a simulation to achieve reasonable results.
The integration requires a very high frequency simulation; and
PNOISE maximum sidebands parameter increases drastically;
resulting in very long simulation times.
For simulations with a larger number of elements (i.e. A complete
chip) PNOISE simulation may still be viable, simulation-time wise.
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Analyzing the Switched
Capacitor Amplifier
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Extends the analysis of the switched capacitor track and hold.
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Analyzing the Switched
Capacitor Amplifier
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Noise sources are identified in each phase, referred to the output
and integrated.
• Sampling Phase
• Evaluation Phase
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Analyzing the Switched
Capacitor Amplifier - Continued
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An analytical expression is reached for the noise behavior of the
switched capacitor amplifier.
Further simplification (identifying the dominatnt noise sources) lets
us arrive at a clear noise optimization strategy.
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Simulating the Switched
Capacitor Amplifier
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Simulation methods derived earlier are utilized to match analytical
equations with simulation results.
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A Milestone in the Thesis
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At this point; having correlated simulation results with our analysis;
we had developed a methodology of simulation for noise in switched
capacitor circuits.
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We then moved on to the actual circuit that we wanted to analyze;
the 14-bit, two-step, successive approximation ADC.
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Noise Model for the Two-Step
SAR ADC - Flowchart
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Noise Model for the
Two-Step SAR ADC
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Three phases are modeled; sampling, amplification and resampling.
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Substituting in the CMOS
Operational Amplifier
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Fully-Differential OPAMP with NMOS input, class AB output stage,
continuous time CMFB.
Parameter
Value
Open Loop
Gain
125 dB
GBW
56MHz
Phase Margin
56 deg.
Power
Consumption
3.13 mW
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Substituting in the CMOS Operational
Amplifier – Adaptive Compensastion
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The capacitve load of the
amplifier changes in the
amplification and resampling
stages.
In the amplification stage, the
opamp is used to provide a
gain of 64; which also
reduces compensation
requirement.
To achieve stability in the
resampling state, and speed
in the amplification state;
adaptive compensation.
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Simulating the Switched Capacitor
Amplifier with the CMOS OPAMP
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Noise floor increases with the added noise of the CMOS OPAMP.
Integrated noise is found to be 10.68uV2, resulting in a 3.3mV effective
noise voltage; lower than one LSB of the converter.
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Simulation Results for the
Two-Step SAR ADC
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Integrated noise is found to be 17.11uV2, resulting in a 4.1mV effective
noise voltage; lower than one LSB of the converter.
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