Design of RF CMOS Low Noise Amplifiers Using a Current Based
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Transcript Design of RF CMOS Low Noise Amplifiers Using a Current Based
Design of RF CMOS Low
Noise Amplifiers Using a
Current Based MOSFET
Model
Virgínia Helena Varotto Baroncini
Oscar da Costa Gouveia Filho
OUTLINE
1.
2.
3.
4.
5.
6.
Introduction
MOSFET Model
High-Frequency Noise Model
LNA Analysis
LNA Design Example
Conclusion
Introduction
• Submicrometer CMOS technology
integration of RF circuits.
allows
the
• Low voltage and low power operation → moderate
inversion
• Model valid from weak to strong inversion
MOSFET MODEL
D
I(VG,VS)
G
I D I F I R I VG ,VS I VG ,VD
I(VG,VD)
IF= forward current
B
IR= reverse current
S
'
Q
IS D
' W
I F R μn C ox
'
2 L nC ox
T
2
T
Q'IS D
2
'
nC
ox T
2
Normalized currents
1 i f (r )
where
and
i f (r )
QIS ( D )
1
t
nC ox
IF
IS
2
'
t W
I S .n.C ox
2 L
are the normalized currents
is the normalization current
Operation Regions of the MOS transistor
ir
103
strong
102 moderate
triode
reverse saturation
ir > 100 if
forward saturation
100
weak
10-1
weak
strong
10-3
10-3
if > 100 ir
10-1 100
102 103
1
if
Small signal parameters
Transconductances
gms
2I s
t
g ms
gm
n
1 if 1
Capacitances
2
C gs WLC ox
3
C gb
1 if 1
1 if 2
1 if 1
n 1
C gs
WLCox
n
2
High- Frequency Noise
Model
Rg
G
S
B
SvRg
D
gmsVsb
Cgb
Sig
Cgs
gmVgb
Sid
S
B
Channel Thermal Noise
4kTμ Q I
S id
L2
1
2
S id 4kTgms
3
1
i
1
f
1 i f 1 1
10-23
Sid (A2/Hz)
10-24
10-25
10-26
10-27
10-28
10-29
10-3
10-2 10-1
100
101
102
103 if
Induced Gate Noise
ωC
2
S ig 4kTδ
gs
5gms
δ ω W L C
8
S ig kT
45
μ0 nT
2
10
10
Sig(A 2 /Hz)
10
10
10
10
10
3
'
ox
1 if
1
1 if
1 if 1
-45
-46
-47
-48
-49
W /L=1000
W /L=2000
W /L=3000
W /L=4000
W /L=5000
-50
-51
10
-3
10
-2
10
-1
0
10
inversion level
10
1
10
2
10
3
4
2
2
LNA Analysis
Cascode LNA with inductive source degeneration
VDD
Ld
Vb
Vin
Lg
M2
M1
LS
Impedance Matching
Lg
Cgb
Cgs
gmbVsb
Zin
Z1
Z1
gmsVgs
Ls
1
2
Ls C gs g m
1
jC gs
1 2
Ls C gs g m
Z1 can be viewed as the parallel of a resistor R with the
capacitance Cgs
Simplified small signal model for the LNA
Lg R 2C 1 2 Lg C
R
Z in
j
2 2 2
1 R C
1 2 R 2C 2
matching is achieved simply by making the real part of Zin equal
to the source resistance and its imaginary part equal to zero.
Rs C gs C gb
Ls
ωT
C gs
Lg
1
ω02 C gb C gs
Definition
Noise Figure
Total output noise
F
Total output noise due to the source
LNA small-signal model for noise calculations
The noise figure can be expressed as a function of if
Noise figure versus W/L for several inversion levels at 2.5 GHz
4
if=15
if=20
if=25
if=30
if=35
3.5
Noise Figure (dB)
3
2.5
2
1.5
1
500
1000
1500
2000
2500
3000
W/L
3500
4000
4500
5000
LNA Design Example
LNA Design Parameters
Resonance frequency
Supply voltage
Length
Source resistance
Noise Figure
2,5 GHz
2,5 V
0,35 m
50
< 2dB
Procedure
1. Choice of the inversion level
if=35
2. Ls for impedance matching
3 n 1 L
Ls RS
4 n T
2
2
1 i f 1 2
1 if 1
2
1 i f 2
1 if 2
1 if 1
3. Transistor width for minimum noise figure
4
if=15
if=20
if=25
if=30
if=35
3.5
Noise Figure (dB)
3
2.5
2
1.5
1
500
1000
1500
2000
2500
3000
W/L
3500
4000
4500
5000
Noise figure versus W/L for several inversion levels at 2.5 GHz
4. Lg to satisfy the resonance frequency
Lg
WLC ox 2 1 i f
2
0
'
1 1 i
2 3n 1
3n 1 i f 1
f
2
1 if 1
5. Ld to adjust the gain and the output resonance frequency
2
LNA Design Results
W/L
W
ID
Rs
Ls
Lg
Ld
1500
525 m
4,1 mA
50
0,7 nH
7,6 nH
2,5 nH
VDD
RLd
Ld
M1
RS
Lg
Vin +Vbias
M2
Ls
Vout
CL
Simulation results
Input impedance
Noise Figure
Conclusions
The
main advantage of this methodology
is that is valid in all regions of the
operation of the MOS transistors;
It is possible to move the operation point
of RF devices from strong inversion to
moderate inversion taking advantage of
higher gm/ID ratio, without degrading the
noise figure;