Transcript 6a-Programmable-devices

DIGITAL SYSTEMS
Programmable devices PLA-PAL
Rudolf Tracht and A.J. Han Vinck
content
• Programmable Logic
– Programmable Logic Array PLA
– Programmable Array Logic PAL
Programmable Logic Array
k product lines
General structure:
–For a ROM, the number
of product terms is k = 2n
NAND
NAND
n-input
m-output
–For a PLA, k < 2n
• A PLA can implement m functions of n variables, where each
function (in SoP form) can have up to k product terms
• PLA is programmed to
• select the literals in each product term
• and select the product terms in each function
Cont’d
• Pre-fabricated building blocks of many NAND gates
"personalized" by making or breaking connections among the gates
programmable array block diagram for sum of products form
• • •
inputs
NAND
array
n
product
terms
k
NAND
array
outputs
• • •
m
Before programming
All possible connections are available before "programming"
Note: conversion to NAND
ab+cd=
((a  b)‘  (c  d)‘)‘
F0
F1
F2
F3
=
=
=
=
A +
A C'
B' C'
B' C
B' C'
+ AB
+ AB
+ A
after programming
A
Note: conversion to NAND
ab+cd=
((a  b)‘  (c  d)‘)‘
F0
F1
F2
F3
=
=
=
=
A +
A C'
B' C'
B' C
B' C'
+ AB
+ AB
+ A
C
B
•Unwanted connections are "blown„
Shared product terms among outputs
example:
F0
F1
F2
F3
=
=
=
=
A +
A C'
B' C'
B' C
B' C'
+ AB
+ AB
+ A
input side:
personality matrix
product
term
AB
B'C
AC'
B'C'
A
inputs
A
B
1
1
–
0
1
–
–
0
1
–
C
–
1
0
0
–
outputs
F0 F1
0
1
0
0
0
1
1
0
1
0
1 = uncomplemented in term
0 = complemented in term
– = does not participate
F2
1
0
0
1
0
F3
0
1
0
0
1
output side:
1 = term connected to output
0 = no connection to output
reuse of terms
PLA
• Two-level AND-OR device
– can be programmed to realize any sum-of-products
• Limitations:
– Number of inputs, outputs, product terms
• Field programmable:
– attractive in a research environment
– Programm can be simulated and changed immediately
ANDing and ORing
Products
Inputs
1
AB
1
A’B’
1
1
A
A’
B
B’
1
1
1
1
1
Example of basic functions
•Multiple functions of A, B
–F1 = A B
–F2 = A + B
–F3 = A' B'
–F4 = A' + B'
–F5 = A xor B
A B
F1 F2 F3 F4 F5
0 0
0 0 1 1 0
0 1
0 1 0 1 1
1 0
0 1 0 1 1
1 1
1 1 0 0 0
A
B
Homework: do the
same for 3 variables
Programmable Aray Logic PAL
limited connections are available before "programming"
–constrained topology
–faster and smaller OR
plane
example BCD to Gray code converter
A
A
0
0
0
0
0
0
0
0
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
1
C
0
0
1
1
0
0
1
1
0
0
1
–
D
0
1
0
1
0
1
0
1
0
1
–
–
W
0
0
0
0
0
0
0
0
1
1
–
–
minimized functions:
W=A
X= B+A
Y = BC‘ + B‘C
Z = C'D + C D'
X
0
0
0
0
1
1
1
1
1
1
–
–
Y
0
0
1
1
1
1
0
0
0
0
–
–
Z
0
1
1
0
0
1
1
0
0
1
–
–
A
0
0
x
1
0
0
x
1
C 0
0
0
x
x
0
x
x
D
0
1
X
1
0
1
X
1
C 0
0
1
X
X
1
X
X
B
B
K-map for W
K-map for X
A
D
A
0
1
X
0
0
1
X
0
C 1
1
0
X
X
0
X
X
D
0
0
X
0
1
1
X
1
C 0
1
0
X
X
1
X
X
B
B
K-map for Y
K-map for Z
D
recall
•
Two dimensional array of 1s and 0s
– entry (row) is called a "word"
– width of row = word-size
– index is called an "address"
– address is input
– selected word is output
word lines (only one
is active – decoder is
just right for this)
1
1
1
1
n
2 -1
decoder
i
word[i] = 0011
j
word[j] = 1010
0
internal organization
0
n-1
Address
bit lines (normally pulled to 1 through
resistor – selectively connected to 0
by word line controlled switches)
ROM vs. PLA
•
ROM approach advantageous when
– design time is short (no need to minimize output functions)
– most input combinations are needed (e.g., code converters)
– little sharing of product terms among output functions
•
ROM problems
– size doubles for each additional input
– can't exploit don't cares
•
PLA approach advantageous when
– design tools are available for multi-output minimization
– there are relatively few unique minterm combinations
– many minterms are shared among the output functions
•
PAL problems
– constrained fan-ins on OR plane
structures for two-level logic
•
ROM – full AND plane, general OR plane
– cheap (high-volume component)
– can implement any function of n inputs
– medium speed
•
PAL – programmable AND plane, fixed OR plane
– intermediate cost
– can implement functions limited by number of terms
– high speed (only one programmable plane that is much smaller than
ROM's decoder
•
PLA – programmable AND and OR planes
– most expensive (most complex in design, need more sophisticated tools)
– can implement any function up to a product term limit
– slow (two programmable planes)