Transcript 7 -- ICsx

‫طراحی مدارهای منطقی‬
‫دانشگاه آزاد اسالمی واحد پرند‬
‫نیمسال دوم ‪93-92‬‬
‫طراحی مدارهای منطقی‬
‫دانشگاه آزاد اسالمی واحد پرند‬
‫‪ICs‬‬
‫)‪(Mux, Decoder, ROM, PLA, PAL‬‬
Where are we?
 Far now  Basic logic design
 More complex integrated circuits (ICs)
 Integrated circuits
 Small-Scale Integration (SSI)
• Packages  typically contain one to four gates, six inverters,
or one or two flip-flops
 Medium-Scale Integration (MSI)
• Like  adders, multiplexers, decoders, registers, and counters
• Package  12 to 100 gates
 Large-Scale Integration (LSI)
• Package  100 to a few thousand gates
 Very-Large-Scale Integration (VLSI)
• Packge  Several thousand gates or more
Contents
 Multiplexer
 Three-state buffer
 Decoder, Encoder
 ROM
 PLD
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
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
PLA
PAL
CPLD
FPGA
Multiplexer (MUX)
Multiplexer
 A group of data inputs
 A group of control inputs
 The control inputs are used to select one of the data
inputs and connect it to the output terminal
Multiplexer (MUX)
Multiplexer
Multiplexer (MUX)
Multiplexer 4:1  With Mux 2:1
Multiplexer 8:1  With Mux 2:1
Multiplexer (MUX)
 Applications
 Data selector
=
Multiplexer (MUX)
 Applications
 Implement general logic functions
Multiplexer (MUX)
 Multiplexer
 High/low output
 High/low enable
Three-State Buffer
 Buffer
 A gate output can only be connected to a limited number of
other device inputs without degrading the performance of a
digital system.
 A simple buffer may be used to increase the driving capability
of a gate output
Three-State Buffer
 Three-State Buffer = Tri-State Buffer
 Normally, a logic circuit will not operate correctly if the outputs
of two or more gates or other logic devices are directly
connected to each other
 Use of three-state logic permits the outputs of two or more
gates or other logic devices to be connected together
 B open  High-impedance = Hi-Z
Three-State Buffer
 Three-State Buffer = Tri-State Buffer
Three-State Buffer
 Data selection
Three-State Buffer
 4-Bit Adder with Four Sources for One Operand
 Integrated Circuit with Bi-Directional Input-Output Pin
Decoder/Encoder
 Decoder  n to 2n
 Generates all 2n minterms/maxterms of the three input
variables
 Exactly one of the output lines will be 1 for each
combination of the values of the input variables
Decoder/Encoder
 4 to 10 Decoder
Decoder/Encoder
 Example
Decoder/Encoder
 Encoder  Reverse function of decoder
 8-to-3 Priority Encoder
ROM  Read-Only Memory
 An array of semiconductor devices that are interconnected to
store an array of binary data
 Data can be read out whenever desired, but the stored data
cannot be changed under normal operating conditions
ROM  Read-Only Memory
 Typical  32 ×4 , 512 ×8
ROM  Read-Only Memory
 One possible internal structure of 8 ×4 ROM
ROM  Read-Only Memory
 Example  Multiple-output combinatorial circuits
PLD  Programmable Logic Device
 PLD  a general name for a digital integrated circuit
 capable of being programmed to provide a variety of different logic
functions
 Changes in the design can easily be made by changing the
programming of the PLD without having to change the wiring in
the system
PLD  Programmable Logic Device
PLA  Programmable Logic Array
 PLA with n inputs and m outputs can realize
• m functions of n variables
PLD  Programmable Logic Device
PLA  Programmable Logic Array
PLD  Programmable Logic Device
PLA  Programmable Logic Array
PLD  Programmable Logic Device
PAL  Programmable Array Logic
 Special case of PLA
• AND array is programmable and the OR array is fixed
• Less expensive than PLA
• Easier to program
PLD  Programmable Logic Device
PAL  Programmable Array Logic
 Example  Full-Adder
PLA vs. PAL vs. ROM
 PLA/PAL  AND array
 ROM  decoder
 PLA/PAL  SOP
 ROM  Truth table
AND
OR
PLA
Programmable
Programmable
PAL
Programmable
Fixed
ROM
Fixed
Programmable