Transcript 360N: Computer Architecture Spring 2005

Outline
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Memory characteristics
SRAM
Content-addressable memory details
DRAM
© Derek Chiou & Mattan Erez
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What Memory Should I Use?
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Depends on access characteristics
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How often is it written?
How often is it accessed in general?
How fast should the accesses be?
 Latency? Bandwidth?
What should the capacity be?
 Bytes? Kilobytes? Megabytes? Gigabytes? Terbytes?
How long should the data last?
 Microseconds? Seconds? Years? Decades?
Granularity of access
Cost
 Dollars, watts or joules, …
Different memories optimized for different access types
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Memory Types
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ROM (non-volatile Read Only Memory)
RAM (volatile, Random Access Memory)
“Disk”
Non-mainstream
Really misnomers today
RAM is often not truly random access
ROM is writable, just more slowly than RAM
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Random Access Memory (RAM)
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Static RAM (SRAM)
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Dynamic RAM (DRAM)
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“Static” indicates that as long as you apply power, the value
will be maintained
6 transistors/bit
What does dynamic mean?
Capacitor stores data (1 cap + 1 transistor/bit)
Interfaces
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DDR – double data rate
Burst mode – most DRAMs have a burst of at least 4 (now 8)
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SRAM
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SRAM Cell (6T)
word line
=
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SRAM Array
b0
b0 b1
b1 b2
b2 b3
b3
word line 0
word line 1
word line 2
word line 3
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Accessing SRAM
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Can read/write (modulo bus turnaround) every cycle
Generally 1 cycle latency (could be longer based on
pipelining)
Large SRAMs are slower than smaller SRAMs
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DRAM
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DRAM Cell
What happens when you read?
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DRAM Cell
What happens when you read?
Infineon 80nm
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DRAM Refresh
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Capacitor holding value leaks, eventually you will lose
information (everything turns to 0)
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How do you maintain the values in DRAM?
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Simplified DRAM
Internal Structure
Row
RAS
Column
Addr
CAS
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Simplified DRAM Internal Structure
Row
RAS
Column
CAS
Addr
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DRAM Array
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Accessing DRAM (RAS)
Simplified Bank State Diagram
act
rd
pre
wr
request
Row decoder
bank 0
DRAM
Memory array
Sense amplifier
Operation Resource Utilization
Cycle
Column decoder
Activate Row
data
Request
Data
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Accessing DRAM (CAS)
Simplified Bank State Diagram
act
rd
pre
wr
request
Row decoder
bank 0
DRAM
Memory array
Sense amplifier
Operation Resource Utilization
Cycle
Column decoder
Read Row
data
Request
Data
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Accessing DRAM (re-writing “lost” data)
Simplified Bank State Diagram
act
rd
pre
wr
request
Row decoder
bank 0
DRAM
Memory array
Sense amplifier
Operation Resource Utilization
Cycle
Column decoder
Precharge Row
data
Request
Data
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DRAM RAS/CAS
Summary
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Assert RAS to specify row address
Assert CAS to specify column address
Why separate RAS/CAS?
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Can pulse CAS to read more from the same row
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Faster
Implications?
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Called Fast Page Mode
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What to do while
waiting for Act/Pre/…?
bank
bank
n-1
1
0
request
Row decoder
DRAM
Memory array
Sense amplifier
Column decoder
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DRAM Hierarchy/Banks
Row
RAS
Column
CAS
Bank[1:0]
Why have banks?
Cannot access banks back-to-back. Why?
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Memory Interfaces
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How much data per column command?
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SDRAM
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Interface width (x4, x8, …)
 How much data per bus transfer
 Note: each column DRAM address refers to width bits
Burst length (4, 8, …)
 How many bus transfers per CAS
Synchronous DRAM – more when we discuss buses
DDRx
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Double-data rate – multiple data transfers per clock (rising and
falling edge, or even faster)
DDR, then DDR2, then DDR3 – just different standards for
defining sizing, timing, and electrical parameters
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Tradeoffs: SRAM vs DRAM
Criteria
SRAM
DRAM
Speed
Low Latency
High
Bandwidth
Static
Yes
No
Access
Easy
Harder
Process
Logic
DRAM
Refresh
No
Yes
Density
Low
High
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“Experimental” Memory Technology
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Not yet mainstream, but making headway
Embedded DRAM
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STT-RAM – Spin torque transfer RAM
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DRAM in logic process, integrated with the processor
In between SRAM and DRAM in terms of properties
Based on Spintronics – manipulation of electron spins
Works like 60’s “core memory”, but nano-sized
“best of all worlds”, but still low density and experimental
PC-RAM – Phase-change RAM
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Based on heat-related changes to physical structure of cell
FLASH replacement
May replace DRAM
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Memory Modules (DIMMs)
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Dual In-line Memory Module (DIMM)
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Multiple chips on independent module
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Standard memory interface today
Easy to build and maintain systems
DIMMs have one or more “ranks”
Rank is multiple chips that share same CE
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Memory Modules (DIMMs)
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Dual In-line Memory Module (DIMM)
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Multiple chips on independent module
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Standard memory interface today
Easy to build and maintain systems
DIMMs have one or more “ranks”
Rank is multiple chips that share same CE
MAR
10
logic
CE
addr
WE
x8
CE
WE
x8
8
CE
WE
x8
8
CE
WE
x8
8
Width?
Ranks?
Chips/rank?
8
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