Transcript Physical Memory and Physical Addressing

Physical Memory and
Physical Addressing
By:
Preeti Mudda
Prof: Dr. Sin-Min Lee
CS147 Computer Organization and
Architecture
Agenda
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Physical Memory
Random Access Memory
Two Types of Ram
Dynamic RAM
Static RAM
Physical Address
Word Size
Byte Alignment
Physical Memory
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Physical memory is the
main memory that has
direct/indirect access to
CPU
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Physical memory mainly
consists of RAM
Random Access Memory
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Random Access Memory (RAM): Any data
could be accessed in a constant time regardless
of its physical location.
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Two Types of RAM:
 DRAM – Dynamic Random Access Memory
 SRAM – Static Random Access Memory
Dynamic Random Access Memory
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DRAM is an integrated circuit.
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Millions of transistors and capacitors are paired
together to create an array of memory cells
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Capacitor holds the bit information
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Transistors behaves like a switch which lets the
control circuitry to control the state of the memory
chip by reading or changing the capacitor state.
DRAM Architecture
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DRAM Chips are large and rectangular
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Arrays of memory cells
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Support logic- used for reading and
writing data in arrays
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Refresh Circuitry- maintain the integrity of
the stored data by periodically refreshing
the memory cells
http://www.cs.duke.edu/courses/fall98/cps104/lectures/week10-l2/sld024.htm
DRAM
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Memory cell represents single bit data (logic
1/logic 0)
Cells are imprinted on silicon wafer
Array of columns (bitlines)
Array of rows (wordlines)
Intersection of bitline and wordline is the
address of the memory cell
Support Circuitry
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Sense amplifiers: Amplifies signal or charge
detected on the memory cell
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Address logic: Select rows and columns
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Row Address Select(RAS) and Column Address
Select(CAS): Latch and resolve the row and
column addresses. It initiates or terminates the
read/write operation
Support Circuitry
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Read /Write circuitry: Store or read the
information in the memory cell
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Internals Counters: Keep track of the refresh
sequence or initiate refresh cycle
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Output Enable logic: Prevents the data from
displaying it unnecessarily.
DRAM Read timing
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Row Address Strobe (RAS):
 Latch row address and initiate the memory cycle.
 It is required at the beginning of every operation.
 To enable RAS the voltage transition should be from high to
low voltage.
 RAS is an active low and it should maintain low voltage as
long as RAS is required
 Complete memory cycle: RAS must active for minimum
amount time and also inactive for minimum amount of time.
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Column Address Strobe:
 Initiate Read/Write Operation
 CAS must be active before RAS for refresh cycle.
DRAM Timing
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Write Enable(WE):
 Write enable signal used to choose for read/write operation.
 Low voltage-level signifies a write operation
 High-voltage level signifies a read operation.
Output Enable (OE):
 This control signal is used to prevent displaying the output while
read operation.
 The control signal is grounded when write operation is selected.
Data IN/OUT(DQs):
 DQ pins used for input and output
http://www.cs.duke.edu/courses/fall98/cps104/lectures/week10-l2/sld024.htm
http://www.cs.duke.edu/courses/fall98/cps104/lectures/week10-l2/sld024.htm
Steps to access a cell in DRAM
Static RAM
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Type of semiconductor memory
No need to refresh frequently
Uses six MOFETS to store each memory
bit
Size: SRAM has m address lines and n
data lines: 2^m words.
SRAM
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Three different states:
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Standby: The circuit is idle
Reading: Reading the data which has been
requested
Writing: Writing the data on to the memory
SRAM
http://www.cs.duke.edu/courses/fall98/cps104/lectures/week10-l2/sld016.htm
SRAM
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Reading:
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WE_L is disasserted (H), OE_L
is asserted (L)
D: data output pin
Writing:
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WE_L is asserted
(L) where as OE_L
is dis-asserted (H).
D: Data input pin.
http://www.cs.duke.edu/courses/fall98/cps104/lectures/week10-l2/sld018.htm
Physical Address
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Physical address is a memory address that is
stored in the form of binary number
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It is electronically represented on the computer
address bus circuitry
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Through this data bus is enabled to access
particular storage from the main memory cell
Physical Memory and Word Size
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Bits of physical memory are divided into
blocks of N bits
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Terminology
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– Group of N bits is called a word
– N is known as the width of a word or the word
size
Physical Memory Addresses
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Each word of memory is assigned a unique
number known as a physical memory
address
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Programmer imagines physical memory to be
an array of words
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Note: entire word must be transferred
Choosing A Word Size
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Larger word size
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Implemented with more parallel wires
Results in higher performance
Higher cost
Note: architect usually designs all parts of
computer to use
one size for:
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Memory word
Integer (general-purpose registers)
Byte Addressing
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View of memory presented to processor
Each byte of memory assigned an address
Convenient for programmers
Underlying memory can still use word
addressing
Translation Between Byte And
Word Addresses
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Performed by intelligent memory controller
CPU can use byte addresses (convenient)
Physical memory can use word addresses
(efficient)
Byte Alignment
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Refers to integer storage in memory
In some architectures
– Integer in memory must correspond to word
in underlying physical memory
In other architectures
– Integer can be unaligned, but fetch and
store operations are much slower
Memory Size And Address
Space
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Size of address limits maximum memory
Example: 32-bit address can represent
2^32 = 4,294,967,296
unique addresses
Known as address space
Note: word addressing allows larger memory
than byte addressing
Resources
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Physical Memory:
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IBM article “Understanding DRAM operation”
CS-Duke Lecture notes: Memory Systems
Wikipedia
Howstuffworks website
Physical Address:
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http://www.eecs.wsu.edu/~hauser/teaching/ArchF07/handouts/Chapter10.pdf
Wikipedia