Transcript Seeon_ASIC_May15v2x

DCD submission plan
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Changes in design (present status):
Change sampling of TDI for global and pixel register to positive edge
Add fast parallel sampling mode for easier needle card tests (maybe)
Improve test DAC resolution (?) by adding additional DAC
Programmable LVDS output current (or just larger)
Protection diodes should be on VDDD for digital
Investigate power up problem
Add transmission switch to monitor (now only PMOS)
Check the voltage drop on power rail – connect gate of the NMOS sources only in
one point
Reduce RefIn current
Try to connect DAC Dump and SF VDDA to RefIn
Separated bias DACs for up and down bias
Spare ADCs
Alternative - Current through bias line
Redo protection diode, current drain/split nwell
Ipdac 60uA full range
SubIn 4 times or additional DAC
Introduce 15k Feedback resistor setting – low gain mode
Variable digital test patterns (?)
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD submission plan
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Simulations:
ADC full/CMC+Comparator corner, mismatch, drop
Measurements:
RefIn/ALow vary whole chip
Current mismatch
Repeat after irradiation
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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JTAG and slow controll
Pixel Register
PixelSel
P_Shift, P_Rb, P_Ld
PixelSel
ShiftDR, CaptureDR, UpdateDR
Address
Global Register
GlobalSel
G_Shift, G_Rb, G_Ld
Digital Block
GlobalSel
State M.
TMS
ShiftDR, CaptureDR, UpdateDR
TDO
PreLoad
Data Register
CaptureIn
LatchOut
DO0(7:0),DI0(1:0),…,DI3(1:0),SYNC_RES,CLK,RetCLK,TestInjEn,DO4(7:0),…,DI7(1:0)
In
Out
CaptureIn
Cont. Signals
ShiftDR, CaptureDR, UpdateDR
Commands
Instruction Register
ExtTest OR PreLoad
LatchOut
ExtTest
Pads
i
FF
i
Res!
ShiftIR, CaptureIR, UpdateIR
o
ShiftIR
The other if not ShiftIR
Bitck Res
TestMode
TestMode
TDI
ID Register
TestPads
FF
IDSel
ShiftDR&IDSel
Readout Reg
CaptureIn
TCK
Full custom
latches
19th Intl. Workshop on DEPFET Detectors andLd
Applications,
Seeon,
May, 2015
CaptureIn
o
Readout
FF
FF
Bypass
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DCD Measurements
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19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD Measurements
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19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD submission plan
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VDDA
VDDA
This makes current GNDA constant always
Source
~300uA
AmpInCM
RefIn
SF AmpOut
AmpIn
RefIn Current isn‘t constant
This makes NMOS scs independent on GNDA noise
~60uA
RefIn
VDDA
240uA max
Source
GNDA
Gate
RefIn
RefIn
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD submission plan
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DAC
Mirror
d
d
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD submission plan
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DAC
DAC
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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Origin of offset
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Possibility: transistor mismatch – fix in the next chip: make the layout in a better way e.g. the
transistors bigger
Additionally, there may be a systematic offset in comparator that adds to the mismatch
Notice also: two output nodes are not on perfectly same potential
Original UI converter connected to amplifier input, copy UI converter to RefIn – this explains RefIn
dependence
Reduce RefIn voltage drop!
Low
PFB
PFB
24u
24u
RefFB
RefFB
RefIn
RefIn
24u
Sc2
TooLow
24u
24u
Sc2
Sc2
26u
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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SWITCHER Status
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SWITCHER
Irradiation of latest SWITCHER has been done at KIT (dose 31 MRad)
The chip works after the irradiation
Bumping: bumping so far done in HD-lab, this works well for prototyping but is slow for production
Bumping with the required pitch (150 μm) is not offered by the vendor (AMS/IBM)
Solution: Company Pactec can place underbump metallization (ENIG) and solder bumps on single
dies
SWITCHER submission planned for end of May 2015
Improvements: faster clear driver
Separated control of the termination resistance for serial input (should be always on) and for the
other fast inputs
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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Rise Time Measurements – irradiated chip
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Irradiation to 21MRad – 150pF load
We need to increase size of the power transistors
Can be done, but the chip size will increase by 100um
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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Simulation
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Simulation of clear pulse with 150pF load
Output transistors 3 time wider
20ns
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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Backup Slides
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
DCDBPip
TIA
ADC
200 µm
5 mm
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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ASICs
Ivan Peric
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
DCD
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
KIT
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The development/production of DCD and SWITCHER chips will be done from middle
of 2015 at KIT
ASIC and detector laboratory (ADL) at the Institute for Data Processing and
Electronics (IPE)
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCDBPip
TIA
ADC
200 µm
5 mm
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD
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DCD chip contains 256 channels, each channel has a DEPFET current receiver
(trans-impedance amplifier) and an eight bit ADC
DCD specifications:
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Required number of channels (256)
Sampling rate of about 100ns
Radiation tolerance up to a dose of about 20MRad
Noise which should allow good detection efficiency (~ 200e – SNR ~ 25)
Power consumption not too high, current consumption ~ 1A
Resolution 10 bits (2-bit offset correction DAC and 8-bit ADC)
Dynamic range of up to 90uA (low gain mode 115nA/LSB) which should be enough to
cope with DEPFET current that has signal and mismatch part
Non-standard fabrication process. After fabrication of standard layers (FEOL, BEOL)
the chips are sent to another company which adds one extra layer, bump pads and
bumps.
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD
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Testing of these single dies is difficult
Due to space constrains if was not possible to implement standard differential pads –
the chip’s IOs are not compatible with FPGA
Since the chip does not have wire bonds, it must be mounted onto adapter
Another ASIC must be used to convert DCD IO format to the standard one
Difficult characterization
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD
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Different tests setups
DCD
Tests on probe station
Test with DEPFET or with test signal sources
DCD
DCDRO
Sensor
To FPGA
adapter
PCB
Tests on hybrid4 with DCDRO
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD
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Different tests setups
Test with DEPFET or with test signal sources
Irradiation tests
DCD
DHP
Sensor
adapter
PCB
Tests on hybrid5 with DHP
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD
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EMCM
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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DCD tests on single chip PCB
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
Chip #1 Test all ADCs
first ADC’s Noise
150
INL of first ADC
INL [ADU]
Noise [ADU]
ADU
0.8
0.7
100
DNL of first ADC
DNL [ADU]
ADC Characterization
100
80
3
2.5
60
0.6
40
50
2
0.5
20
0.4
0
1.5
0
0.3
-20
0.2
-40
-50
1
 10
5
10
15
20
25
Gain of All ADCs
 10
5
10
15
20
25
30
90
80
 10
0
Mean Noise of All ADCs
100
Noise [ADU]
Gain [nA/ADU]
0
0
30
-80
-6
5
10
15
20
25
-6
1.4
10
9
70
12
14
16
18
20
22
24
-6
26
DNL of All ADCs
10
1.2
 10
0
30
Peak-to-Peak INL of All ADCs
INL [ADU]
0
0.5
-60
0.1
-6
DNL [ADU]
-100
10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
60
0.8
50
40
0.6
30
0.4
20
0.2
40
60
80
100
120
Gain vs. ADC Position
78
14
40
60
80
100
120
Mean Noise vs. ADC Position
80
DCDB physical ADC location
16
20
76
12
16
1.8
1.6
12
74
10
72
8
70
68
6
10
1.2
8
1
0.8
6
4
0
62
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R9L 9R 10L10R11 11 12 12 13L13R14 14 15L15R
L R L R
L R
60
40
60
80
100
120
16
9
14
8
10
6
8
5
4
6
0
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L 13R14 14 15L 15R
L R L R
L R
0
60
80
100
120
16
10
9
14
8
7
10
6
8
5
4
6
3
4
0.2
40
12
7
3
4
0.4
2
20
DNL vs. ADC Position
10
0.6
64
2
20
12
1.4
66
4
0
0
Peak-to-Peak INL vs. ADC Position
2
14
1
0
0
DCDB physical ADC location
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0
0
DCDB physical ADC location
0
0
1
DCDB physical ADC location
10
2
2
0
1
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L13R14 14 15L15R
L R L R
L R
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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2
2
0
1
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L 13R14 14 15L 15R
L R L R
L R
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25
Chip #1 Test all ADCs
ADC
… characteristics
Noise of the first ADC
Deviation from mean for every input
first ADC’s Noise
150
INL of first ADC
0.8
INL [ADU]
Noise [ADU]
0.7
100
DNL of first ADC
DNL: code difference for two consecutive inputs
(first ADC)
DNL [ADU]
ADC Characterization
ADU
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100
80
3
2.5
60
0.6
40
50
2
0.5
20
0.4
0
-20
-50
-40
5
10
15
20
25
Gain of All ADCs
 10
5
10
15
20
25
30
Noise [ADU]
Gain (nA/LSB)
80
1.4
 10
0
5
10
15
20
25
-6
 10
0
30
10
12
14
16
18
20
22
24
-6
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INL (peak to peak for all inputs)
Mean Noise of All ADCs
100
90
0
0
30
-80
-6
Peak-to-Peak INL of All ADCs
Average noise (LSB)
DNL of All ADCs
10
DNL [ADU]
 10
0
0.5
-60
0.1
-6
INL [ADU]
-100
1
INL of the first ADC
Deviation from linear fit for every input
0.2
Gain [nA/ADU]
1.5
0
0.3
9
1.2
70
10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
DNL (peak to peak for all inputs)
1
60
0.8
50
40
0.6
30
0.4
20
0.2
20
40
60
80
100
120
DCDB physical ADC location
78
76
12
80
100
120
16
2
1.8
14
1.6
12
74
10
60
8
70
68
6
10
1.2
8
1
0.8
6
66
4
4
0
62
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R9L 9R 10L10R11 11 12 12 13L13R14 14 15L15R
L R L R
L R
60
40
60
80
100
120
Peak-to-Peak INL vs. ADC Position
16
10
9
14
8
10
6
8
5
4
6
4
0
0.2
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L 13R14 14 15L 15R
L R L R
L R
0
40
60
80
100
120
DNL vs. ADC position
DNL vs. ADC Position
16
10
9
14
8
7
10
6
8
5
4
6
3
3
4
0.4
2
20
12
7
0.6
64
2
20
12
1.4
Gain vs. ADC position
72
0
0
INL vs. ADC position
Mean Noise vs. ADC Position
80
14
40
Noise vs. ADC position
Gain vs. ADC Position
16
20
1
0
0
DCDB physical ADC location
All ADCs:
0
0
DCDB physical ADC location
0
0
1
DCDB physical ADC location
10
2
2
0
1
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L13R14 14 15L15R
L R L R
L R
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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2
2
0
1
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L 13R14 14 15L 15R
L R L R
L R
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Chip #1 Test all ADCs
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Several ADCs show higher noise (out of 128 tested)
90
80
1.4
Bad ADCs
1.2
70
DNL of All ADCs
10
DNL [ADU]
100
Peak-to-Peak INL of All ADCs
INL [ADU]
Mean Noise of All ADCs
Noise [ADU]
Gain [nA/ADU]
Gain of All ADCs
9
10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
1
60
0.8
50
40
0.6
30
0.4
20
0.2
10
0
0
20
40
60
80
100
120
0
0
20
40
60
80
100
120
0
0
20
40
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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80
100
120
0
0
20
40
60
80
100
120
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Chip #1 Test all ADCs
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Noise of the ADC: ~1.3LSB (210e @ gq 450pA/e)
INL the „bad“ ADC: ~5.3LSB
ADC gain 73nA/LSB
Noise floor: ~0.58LSB (92e @ gq 450pA/e)
90
80
1.4
1.2
70
DNL of All ADCs
10
DNL [ADU]
100
Peak-to-Peak INL of All ADCs
INL [ADU]
Mean Noise of All ADCs
Noise [ADU]
Gain [nA/ADU]
Gain of All ADCs
9
10
9
8
8
7
7
6
6
5
5
1
60
3LSBs
0.8
50
40
0.6
4
30
4
3LSB
3
3
2
2
1
1
0.4
20
0.2
10
0
0
20
40
60
80
100
120
0
0
20
40
60
80
100
120
0
0
20
40
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
60
80
100
120
0
0
20
40
60
80
100
120
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Chip #2 test all ADCs – fit (-100 to 125)
first ADC’s Noise
150
Noise [ADU]
100
INL of first ADC
1
DNL of first ADC
DNL [ADU]
ADC Characterization
INL [ADU]
…
ADU
•
80
60
40
1.6
0.8
50
20
1.4
0
0.6
2
1.8
1.2
0
0.4
-20
1
-40
0.8
-50
0.6
-60
0.2
-100
0.4
-80
0.2
-100
10
15
20
25
-6
Gain of All ADCs
 10
5
10
15
20
25
-6
90
80
 10
30
0
Mean Noise of All ADCs
100
Noise [ADU]
Gain [nA/ADU]
0
0
30
5
10
15
20
25
-6
1.4
6
70
8
10
12
14
16
18
20
22
-6
24
DNL of All ADCs
5
4.5
1.2
 10
0
30
Peak-to-Peak INL of All ADCs
INL [ADU]
5
DNL [ADU]
 10
0
10
9
4
8
3.5
7
3
6
2.5
5
2
4
1.5
3
1
2
1
60
0.8
50
40
0.6
30
0.4
20
0.2
0.5
40
60
80
100
Gain vs. ADC Position
78
14
40
60
80
100
Mean Noise vs. ADC Position
80
DCDB physical ADC location
16
20
76
12
10
72
8
70
68
6
20
40
60
80
100
16
1.4
14
4.5
14
1.2
4
12
1
10
0.8
3
8
0.6
6
2.5
2
6
0.4
4
0
62
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R9L 9R 10L10R11 11 12 12 13L13R14 14 15L15R
L R L R
L R
60
60
80
100
16
5
4.5
14
4
3.5
10
3
8
2.5
2
6
1.5
4
1.5
4
64
2
40
12
3.5
10
8
20
DNL vs. ADC Position
5
66
4
0
0
Peak-to-Peak INL vs. ADC Position
16
12
74
1
0
0
DCDB physical ADC location
20
0
0
DCDB physical ADC location
0
0
DCDB physical ADC location
10
1
0.2
2
0
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L 13R14 14 15L 15R
L R L R
L R
0
2
0
0.5
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L13R14 14 15L15R
L R L R
L R
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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1
2
0
0.5
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L 13R14 14 15L 15R
L R L R
L R
0
29
Chip #2 Test all ADCs
•
Another chip: no bad ADCs – probably due to more careful optimization of bias parameters
ADC gain 72nA/LSB
Noise: ~0.55LSB
90
80
1.4
1.2
70
DNL of All ADCs
5
DNL [ADU]
100
Peak-to-Peak INL of All ADCs
INL [ADU]
Mean Noise of All ADCs
Noise [ADU]
Gain [nA/ADU]
Gain of All ADCs
4.5
10
9
4
8
3.5
7
1
60
3
50
40
0.6
30
6
2.5LSB
0.8
2.5
5
2
4
1.5
3
1
2
0.5
1
0.4
20
0.2
10
0
0
20
40
60
80
100
0
0
20
40
60
80
100
0
0
20
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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60
80
100
0
0
20
40
60
80
100
30
DCD tests on EMCM
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
DCD
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•
•
EMCM
All ASICs can be configured and read out, Switcher outputs ok
Small PXD6 matrix connected to DCDPipeline
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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EMCM Tests
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Digital test pattern has been used to tests the digital blocks and the communication
DCD - DHP
Test
pattern
bit
29
30
31
0
1
2
3
7
0
0
0
1
0
0
0
6
1
1
0
0
0
1
1
5
1
1
0
0
0
1
1
4
1
1
0
0
0
1
1
3
1
1
0
0
0
1
1
2
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
1
0
1
1
ADCs
mux
DCD digital block
DHP
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
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EMCM Tests
•
Digital test pattern has been used to tests the digital blocks and the communication
DCD - DHP
250MHz, DCD1, VDDD=1.8V
~/TIMING/15_12_22_D
CDpp0_3/test_pattern_
of_dhpdcd0_bit15_SLD
Y_0.pdf
305MHz, DCD1, VDDD=1.8V
~/TIMING/15_12_22_D
CDpp0_1/test_pattern_
of_dhpdcd0_bit61_SLD
Y_0.pdf
column 223
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
(128ADU 160ADU)
34
EMCM Tests
•
Digital test pattern has been used to tests the digital blocks and the communication
DCD - DHP
305MHz, DCD1, VDDD=1.9V
~/TIMING/15_01_07_D
CDpp0_1/test_pattern_
of_dhpdcd0_bit0_SLDY
_0.pdf
305MHz, DCD4, VDDD=1.9V
PLL_SER_
CLK_DLY=1
~/TIMING/15_01_08_DCDp
p3_2/test_pattern_of_dhpd
cd3_dcd_cmos_clk_dly_0_
pll_ser_clk_dly_1.pdf
✔
column 191
(128ADU 132ADU)
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
35
DCD Measurements
•
Test pattern
bit
29
30
31
0
1
2
3
7
0
0
0
1
0
0
0
6
1
1
0
0
0
1
1
5
1
1
0
0
0
1
1
4
1
1
0
0
0
1
1
3
1
1
0
0
0
1
1
2
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
1
0
1
1
Channel 191
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
36
DCD Measurements
•
Test pattern
DCD
VDD
DCD digital block
Channel 191
Bias block
DCD ck
DCD data
Seen by DHP
Duty cycle
DCD ck
Delayed data DHP
DHP
Synchronized by DHP
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
37
DCD Measurements
•
•
Digital communication works for ~ 99.5% channels
Can be improved (next submissions) by slight resizing of bias currents, delay
elements in DHP and DCD
RLC models of DEPFET needed
•
Ideal
bit
29
30
31
0
1
2
3
7
0
0
0
1
0
0
0
6
1
1
0
0
0
1
1
5
1
1
0
0
0
1
1
4
1
1
0
0
0
1
1
3
1
1
0
0
0
1
1
2
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
1
0
1
1
127
0
-127
127
0
-127
0
127
Realistic
Channel 191
0
127
In DHP - CMOS
Reduced sampling window
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
38
EMCM Tests
•
ADC readout – only one channel has unstable bit 6 (64) (digital problem?)
305MHz, DCD1,
VDDD=1.9V
Column 209
ADU: 30, 31, 32, 33 & 63
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
39
EMCM Tests
•
•
•
ADC characterization
ADCs have been measured using internal- and DHE current source
Only 3 ADCs with slightly higher noise – unstable bit (e.g. bit 5)
Column 52
ADU: 94, 95, 96,
126, 127
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
40
EMCM Tests
•
•
•
•
ADC characterization
Noise measurement with LMU power supply on EMCN
Noise 0.5LSB < 100e
Only one ADC with noise ~ 1.5 LSB
4 DCDs on
daciampbias = 66
dacifbpbias = 80
dacipsource = 88
dacipsource2 = 77
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
41
EMCM Tests
•
ADC characterization
ThHi
ThLo
Cf
Cmp1 Cmp2
Rd
WrB*
Wr*
Sw1
1
DAC
RefNWELL
Iin
WrB
NotRd AND Not Wr
Sw2
4
Sw5
NotWr
En Logic
VAmpPBias
A
3
Sub
Add
2
VPSource
VPSourceCasc
Sw3
SF
AmpLow
24 μA
VFBPBias
RefIn
RefIn
VFBNCasc
RefFB
NotRd
12 μA
VFBNBias (VPSource2)
24 μA
Sw4
TC
To Next Cell
RefIn
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
42
Operation of Matrix
•
•
Light sensitive
Still not optimized
14 rows
/home/hybrid5/ADC_curves/DCD_noise/15_01_
15_parser_DCD3_70th/dcdpp_3_dacvnsubin_7
18 rows
/home/hybrid5/ADC_curves/DCD_noise/15_01_19_pars
er_DCD3_71th/dcdpp_3_dacvnsubin_7
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
43
EMCM Tests
•
Different gain settings
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
44
EMCM Tests
•
Missing code
„missing code“
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
45
Missing Codes
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
ADC unit-cell
•
•
•
•
•
The ADC-unit has two current-memory cells based on two U-I converters A and B
Depending on the input current amplitude (too low or too high), a reference current (4 μA per cell)
will be added or subtracted
The comparison is done in the following way:
Two copies of the current stored in A are made – this is done with the two, layout-identical, UI
converters CL and CH that are connected to the same voltage as A
The goal of this preprocessing is “to compress” the input signal so that it occupies 2x smaller
range.
14u
TooLow
CL
12u+/-4u
10u
TooHi
A
CH
12u+/-4u
B
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
47
Unit-cell characteristics
•
•
The purpose of the comparators is to assure that the reference currents are subtracted/added in
the way so that the result current occupies two times smaller range
Only so, the error in algorithm is small
IOut
-8u
-4u
-2u
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
IIn 8u
48
Unit-cell characteristics with offset
•
•
•
Imagine now that the ThHi threshold is shifted by Ref/4 (2uA) +Delta.
Imagine also that the signal is about Ref/2 (=64) In this case the result of the first comparison is
zero. The result of all other comparisons is TooHigh. This leads to the binary code 64.
Imagine now that signals are within range Ref/2 and Ref/2+Delta. Obviously the binary code are
always 64. This leads to the long code 64.
IOut
-8u
-4u
-2u
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
IIn 8u
49
Bad characteristics causes missing codes
•
Missing codes around 64
IOut
-8u
-4u
-2u
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
IIn 8u
50
Origin of offset
•
•
•
•
•
•
Why does the current offset happen?
Possibility: transistor mismatch – fix in the next chip: make the layout in a better way e.g. the
transistors bigger
Additionally, there may be a systematic offset in comparator that adds to the mismatch
Notice also: two output nodes are not on perfectly same potential
Original UI converter connected to amplifier input, copy UI converter to RefIn – this explains RefIn
dependence
We will verify our theory by measurements of the transistor currents. It is possible to access the
output of one transconductor in every channel from outside.
Low
PFB
PFB
24u
24u
RefFB
RefFB
RefIn
RefIn
24u
Sc2
TooLow
24u
24u
Sc2
Sc2
26u
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
Sc2
51
Monte-Carlo Simulation
•
•
We have started Monte Carlo simulations – according to first simulations mismatch is up to 1.5uA
– which is still smaller than 2uA which produces missing codes.
However, the use of enclosed gates and mirroring can make the models not accurate.
Comparator input current for current memory cell current of 4uA (code 64)
If less than 0 we have a long code
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
52
Unit-cell characteristics
•
•
The purpose of the comparators is to assure that the reference currents are subtracted/added in
the way so that the result current occupies two times smaller range
Only so, the error in algorithm is small
IOut
-8u
-4u
-2u
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
IIn 8u
53
Layout
•
•
•
The NMOS current source has a complicated structure
It is based on enclosed NMOS and a PMOS that should compensate for voltage drops (the simple
version with only NMOS behaved worse on DCD1)
The layout is dense
TooHigh
TooLow
Original cell
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
54
Layout
•
…
Old
New
11u
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
18u
55
Layout
TIA
ADC
200 µm
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
56
Missing codes
•
•
•
•
The problem can be solved by changing of layout, which can be done within one-two
weeks.
Question: Is the long code problem worth of this effort
It reduces dynamic range by ¾
Dynamic range is still 20u which should be ok
„missing code“
20uA
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
57
DCD submission plan
•
•
•
•
•
•
•
•
•
•
•
UMC run on 18. May
Changes in design (present status):
Resize of several transistors in ADC to fix the problem of missing codes
Change sampling of TDI for global and pixel register to positive edge
Add fast parallel sampling mode for easier needle card tests
Improve test DAC resolution
Programmable LVDS output current
Add transmission switch to monitor
Check the voltage drop on power rail – connect gate of the SubIn source only in one
point
VDDA
Try to connect DAC Dump and SF VDDA to RefIn
Separated bias dacs for up and down bias
VDDA
This makes current GNDA constant always
Source
~300uA
AmpInCM
RefIn
SF AmpOut
AmpIn
RefIn Current isn‘t constant
This makes NMOS scs independent on GNDA noise
~60uA
RefIn
VDDA
240uA max
Source
GNDA
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
Gate
58
DCD submission plan
•
•
•
•
•
•
•
•
•
•
•
UMC run on 18. May
Changes in design (present status):
Resize of several transistors in ADC to fix the problem of missing codes
Change sampling of TDI for global and pixel register to positive edge
Add fast parallel sampling mode for easier needle card tests
Improve test DAC resolution
Programmable LVDS output current
Add transmission switch to monitor
Check the voltage drop on power rail – connect gate of the SubIn source only in one
point
VDDA
Try to connect DAC Dump and SF VDDA to RefIn
Separated bias dacs for up and down bias
VDDA
This makes current GNDA constant always
Source
~300uA
AmpInCM
RefIn
SF AmpOut
AmpIn
RefIn Current isn‘t constant
This makes NMOS scs independent on GNDA noise
~60uA
RefIn
VDDA
240uA max
Source
GNDA
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
Gate
59
DCD Conclusions
•
•
•
•
•
•
•
•
DCD has been testes in various ways
All circuits have been tested
Probably the only problem is that usually some number of ADCs have a long code
(mostly +64 but can be -64 or zero).
Our measurements are not consistent - measurements in Heidelberg show no long
codes after optimization, measurements in Munich several channels from 256
affected
Question: is the long-lode issue critical? (It only reduces the dynamic range by 25%
in some channels.) Can the present chip be used for production?
The fix for the long code problem is probably easy – resize of several transistors.
All other issues that we encountered during measurements are to my opinion either
not related to DCD itself or fixed in the DCD pipeline design.
The problems in some channels (unstable bits, wrong digital patterns) are probably
the issue of data transfer from DCD to DHP – large capacitances, not optimized
delays, slow digital IOs
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
60
DCD
•
•
•
•
•
•
•
•
•
•
Do we already have enough measurement results?
 We still did not test a properly working DEPFET module with DCDs…
 Measurements with EMCM show very low noise
 Configuration of all ASICs works well
 The DCD-DHP communication has been tested at somewhat reduced speed.
Tests at full speed are not possible due to PLL/VCO/Delay element issue
We do not have many measurements with long DEPFET lines (and capacitances) on
DCD inputs, however additional capacitance, according to simulation, does not
introduce noise; it is just making the amplifier slower. Notice, a slower amplifier is not
critical, since it equally reduces noise and signal. Signal to noise ratio is the same.
We have performed irradiations of DCD2 and DCDBv2. DCDBPipeline uses exactly
the same circuits, just arranged in different way.
SEU tolerance of 180nm technology with 1.8V power supply is better than the SEU
tolerance of 65nm technology.
The only issue could be the NMOS leakage current in the DCD digital part for the
does range 1-5MRad. We will investigate this
Analog CMC has been tested on modular hybrid
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
61
SWITCHER
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
SWITCHER
•
•
•
SWITCEHR chips generate fast high-voltage pulses of up to 20 V amplitude to activate gate rows
and to clear the internal DEPFET gates.
SWITCHER is implemented in HV AMS 180nm technology.
32 channels with a clear- and a gate-driver each.
SWITCHER in 180nm AMS
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
63
DHP
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
Thank you!
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
DCD Measurements
•
Measure
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
66
DCD Measurements
•
Measure
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
67
DCD Measurements
•
Noise vs. Code
RC
Bias V.
ADC
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
68
Problem of low ADC end
•
•
•
•
•
•
•
•
•
•
•
Problem of low ADC end
M1 current too weak
Resistance Sw too high
Out too low (Amplifier A saturates)
Low VT of PMOS not produced or bad corner – do corner simulation
Try
Increase Sc2
Decrease NMWELL voltage
Increase RefFB voltage
Decrease AmpLow (better Out_low), but increase IPAmp for higher in
In next chip – increase W/L of differential PMOS
Out
PFB
24u
RefFB
Sw
RefIn
Sc2
24u
M1
24u
19th Intl. Workshop on DEPFET Detectors and Applications, Seeon, May, 2015
Sc2
69