Transcript Chapter 1: Fundamentals of Quantitative Design and Analysis

Computer Architecture
A Quantitative Approach, Fifth Edition
Chapter 1
Fundamentals of Quantitative
Design and Analysis
Copyright © 2012, Elsevier Inc. All rights reserved.
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Performance improvements:
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Improvements in semiconductor technology
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Feature size, clock speed
Improvements in computer architectures
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Introduction
Computer Technology
Enabled by High Level Language (HLL) compilers,
UNIX
Lead to RISC architectures
Together have enabled:
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Lightweight computers
Productivity-based managed/interpreted
programming languages
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Move to multi-processor
Introduction
Single Processor Performance
RISC
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Moore’ Law
Exponential Growth – doubling of transistors every couple of year
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Do you want to be a millionaire?
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You double your investment everyday
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Starting investment - one cent.
How long it takes to become a millionaire?
a)
b)
c)
d)
e)
20 days
27 days
37 days
365 days
Lifetime ++
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Do you want to be a millionaire?
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You double your investment everyday
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How long it takes to become a millionaire
a)
b)
c)
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Starting investment - one cent.
20 days
27 days
37 days
One million cents
Millionaire
Billionaire
Doubling transistors every 18 months
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This growth rate is hard to imagine
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Cannot continue to leverage Instruction-Level
parallelism (ILP)
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Single processor performance improvement ended in
2003
New models for performance:
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Introduction
Current Trends in Architecture
Data-level parallelism (DLP)
Thread-level parallelism (TLP)
Request-level parallelism (RLP)
These require explicit restructuring of the
application
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Personal Mobile Device (PMD)
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Desktop Computing
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Emphasis on availability, scalability, throughput
Clusters / Warehouse Scale Computers
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Emphasis on price-performance
Servers
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e.g. start phones, tablet computers
Emphasis on energy efficiency and real-time
Classes of Computers
Classes of Computers
Used for “Software as a Service (SaaS)”
Emphasis on availability and price-performance
Sub-class: Supercomputers, emphasis: floating-point
performance and fast internal networks
Embedded Computers
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Emphasis: price
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Classes of parallelism in applications:
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Data-Level Parallelism (DLP)
Task-Level Parallelism (TLP)
Classes of Computers
Parallelism
Classes of architectural parallelism:
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Instruction-Level Parallelism (ILP)
Vector architectures/Graphic Processor Units (GPUs)
Thread-Level Parallelism
Request-Level Parallelism
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Single instruction stream, single data stream (SISD)
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Single instruction stream, multiple data streams (SIMD)
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Vector architectures
Multimedia extensions
Graphics processor units
Multiple instruction streams, single data stream (MISD)
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Classes of Computers
Flynn’s Taxonomy
No commercial implementation
Multiple instruction streams, multiple data streams
(MIMD)
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Tightly-coupled MIMD
Loosely-coupled MIMD
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“Old” view of computer architecture:
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Instruction Set Architecture (ISA) design
i.e. decisions regarding:
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registers, memory addressing, addressing modes,
instruction operands, available operations, control flow
instructions, instruction encoding
Defining Computer Architecture
Defining Computer Architecture
“Real” computer architecture:
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Specific requirements of the target machine
Design to maximize performance within constraints:
cost, power, and availability
Includes ISA, microarchitecture, hardware
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Correlations To Other Fields
Applications – HTML/XML, Audio, Video, Data Compression, and
many others.
Compilers – Gcc, Intel C++, Visual C++, C#, Java, etc.
Operating Systems – Linux, Windows, Unix, etc.
Computer Architecture – Instruction Set, Memory Hierarchy,
Parallelism, Power efficient design, etc.
Circuits and Physical Devices.
- Advances or demands from one field will drive other fields.
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Integrated circuit technology
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Transistor density: 35%/year
Die size: 10-20%/year
Integration overall: 40-55%/year
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DRAM capacity: 25-40%/year (slowing)
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Flash capacity: 50-60%/year
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Trends in Technology
Trends in Technology
15-20X cheaper/bit than DRAM
Magnetic disk technology: 40%/year
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15-25X cheaper/bit then Flash
300-500X cheaper/bit than DRAM
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Bandwidth or throughput
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Total work done in a given time
10,000-25,000X improvement for processors
300-1200X improvement for memory and disks
Trends in Technology
Bandwidth and Latency
Latency or response time
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Time between start and completion of an event
30-80X improvement for processors
6-8X improvement for memory and disks
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Trends in Technology
Bandwidth and Latency
Log-log plot of bandwidth and latency milestones
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Feature size
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Minimum size of transistor or wire in x or y
dimension
10 microns in 1971 to .032 microns in 2011
Transistor performance scales linearly
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Trends in Technology
Transistors and Wires
Wire delay does not improve with feature size!
Integration density scales quadratically
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Problem: Get power in, get power out
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Thermal Design Power (TDP)
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Characterizes sustained power consumption
Used as target for power supply and cooling system
Lower than peak power, higher than average power
consumption
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Clock rate can be reduced dynamically to limit
power consumption
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Energy per task is often a better measurement
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Trends in Power and Energy
Power and Energy
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Dynamic energy
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Dynamic power
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Transistor switch from 0 -> 1 or 1 -> 0
½ x Capacitive load x Voltage2
Trends in Power and Energy
Dynamic Energy and Power
½ x Capacitive load x Voltage2 x Frequency switched
Reducing clock rate reduces power, not energy
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Intel 80386
consumed ~ 2 W
3.3 GHz Intel
Core i7 consumes
130 W
Heat must be
dissipated from
1.5 x 1.5 cm chip
This is the limit of
what can be
cooled by air
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Trends in Power and Energy
Power
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Techniques for reducing power:
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Do nothing well
Dynamic Voltage-Frequency Scaling
Low power state for DRAM, disks
Overclocking, turning off cores
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Trends in Power and Energy
Reducing Power
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Static power consumption
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Currentstatic x Voltage
Scales with number of transistors
To reduce: power gating – turning off the
power supply to idle circuits to reduce
leakage.
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Trends in Power and Energy
Static Power
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Cost driven down by learning curve
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Yield
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DRAM: price closely tracks cost
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Microprocessors: price depends on
volume
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Trends in Cost
Trends in Cost
10% less for each doubling of volume
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Manufacturing ICs
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Yield: proportion of working dies per wafer
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Intel Core i7 Wafer
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300mm wafer, 280 chips, 32nm technology
Each chip is 20.7 x 10.5 mm
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Integrated circuit
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Bose-Einstein formula:
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Defects per unit area = 0.016-0.057 defects per square cm (2010)
N = process-complexity factor = 11.5-15.5 (40 nm, 2010)
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Trends in Cost
Integrated Circuit Cost
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Dependability
Dependability
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Module reliability
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Mean time to failure (MTTF)
Mean time to repair (MTTR)
Mean time between failures (MTBF) = MTTF + MTTR
Availability = MTTF / MTBF
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Typical performance metrics:
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Speedup of X relative to Y
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Execution timeY / Execution timeX
Execution time
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Response time
Throughput
Measuring Performance
Measuring Performance
Wall clock time: includes all system overheads
CPU time: only computation time
Benchmarks
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Kernels (e.g. matrix multiply)
Toy programs (e.g. sorting)
Synthetic benchmarks (e.g. Dhrystone)
Benchmark suites (e.g. SPEC06fp, TPC-C)
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Benchmark Suites
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Desktop
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SPEC CPU2006: 12 integer, 17 floating-point
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SPECviewperf, SPECapc: graphics benchmarks
Server
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SPEC CPU2006: running multiple copies, SPECrate
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SPECSFS: for NFS performance
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SPECWeb: Web server benchmark
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TPC-x: measure transaction-processing, queries, and decision
making database applications
Embedded Processor
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New area
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EEMBC: EDN Embedded Microprocessor Benchmark Consortium
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SPEC2006 Programs and the Evolution of
the SPEC Benchmarks
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Comparing Performance
n
•
•
Arithmetic Mean:
1
n
 Time
i 1
Weighted Arithmetic Mean:
i
n
 Weight  Time
i
i
i 1
•
Geometric Mean:
n
n
 Execution Time Ratio i
i 1
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Execution time ratio is normalized to a base
machine
Is used to figure out SPECrate
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Comparing Performance
n
Arithmetic
Mean:
1
n
 Time
i
i 1
For Program P1 and P2:
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B is 9.1 times faster than A
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C is 25 times faster than A
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C is 2.75 times faster than B
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Comparing Performance
n
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 Weight  Time
Weighted Arithmetic Mean:
i
i
i 1
Different conclusions can be obtained from
different weight
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Amdahl’s Law
Performance improvement to be gained from
using some faster mode of execution is limited by
the fraction of the time the faster mode can be
used.
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Speedup 
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1
(1  f )  ( f / n)
Where:
f is a fraction of the execution time that can be enhanced
n is the enhancement factor
Example: f = .4, n = 10 => Speedup = 1.56
Total Speedup is limited if only a portion can be
enhanced.
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Amdahl’s Law - example
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Amdahl’s law is useful for comparing overall performance of two design
alternatives.
Example:
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Floating-point (FP) operations consume 50% of the execution time
of a graphics application. FP square root (FPSQRT) is used 20% of
the time.
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Improve FPSQR operation execution by 10 times
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Speedup = 1 / ((1-0.2) + 0.2/10) = 1.22
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Improve all FP operations by 1.6 times
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Speedup = 1 / ((1-0.5) + 0.5/1.6) = 1.23
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Improving the performance of the FP operations overall is slightly
better because of the higher frequency.
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CPU Performance Equation
CPU Time  InstructionCount  CyclePerInst  CycleTime
 InstructionCount  CyclePerInst  1 / ClockRate
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Clock Cycle Time: Hardware technology and organization
CPI: Organization and Instruction Set Architecture (ISA)
Instruction Count: ISA and compiler technology
We will focus more on the organization issues
Many performance enhancing techniques improves one with
small/predictable impacts on the other two.
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Example
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Parameters:
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FP operations (including FPSQR) = 25%
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CPI for FP operations = 4; CPI for others = 1.33
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Frequency of FPSQR = 2%; CPI of FPSQR = 20
Compare 2 designs:
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Decrease CPI of FPSQR to 2, or CPI of all FP to 2.5
n
CPI orig   CPI i 
i 1
IC i
 (4  25%)  (1.33  75%)  2.0
Total IC
CPI newFPSQR  CPI orig  2%  (CPIoldFPSQR CPInewFPSQR)
 2.0  2%  (20  2)  1.64
CPInewFP  (75% 1.33)  (25%  2.5)  1.625
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Principle of Locality
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The most important program property
Programs tend to reuse data and instructions they have used recently.
A rule of thumb: a program spends 90% of its execution time in only 10% of
the code.
Predict program’s action in the near future based on its accesses in the
recent past.
Temporal locality: recently accessed items are likely to be accessed in the
near future.
Spatial locality: items whose addresses are near one another tend to be
referenced close together in time.
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Take Advantage of Parallelism
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e.g. multiple processors, disks, memory banks,
pipelining, multiple functional units
Principle of Locality
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Principles
Principles of Computer Design
Reuse of data and instructions
Focus on the Common Case
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Amdahl’s Law
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Principles
Principles of Computer Design
The Processor Performance Equation
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Principles
Principles of Computer Design
Different instruction types having different
CPIs
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Figure 1.13 Photograph of an Intel Core i7 microprocessor die, which is evaluated in
Chapters 2 through 5. The dimensions are 18.9 mm by 13.6 mm (257 mm2) in a 45 nm
process. (Courtesy Intel.)
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Figure 1.14 Floorplan of Core i7 die in Figure 1.13 on left with close-up of floorplan of
second core on right.
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Performance, Price-Performance (SPEC)
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Performance, Price-Performance (TPC-C)
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Misc. Items
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Check SPEC web site for more information, http://www.spec.org
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Read Fallacies and Pitfalls
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For example,
InstCount
ClockRate
MIPS 

6
ExecTime10
CPI 106
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MIPS is an accurate measure for comparing performance among
computers is a Fallacy
MIPS is dependent on the instruction set. Difficult to compare MIPS of
computers with different instruction sets.
MIPS varies between programs on the same computer.
MIPS can vary inversely to performance!! (consider a machine with
floating point hardware vs. software floating point routings)
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Example Using MIPS
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Instruction distribution:
 ALU: 43%, 1 cycle/inst
 Load: 21%, 2 cycle/inst
 Store: 12%, 2 cycle/inst
 Branch: 24%, 2 cycle/inst
Optimization compiler reduces 50% of ALU
•
CPI unoptimized  1  .43  2  .21  2  .12  2  .24  1.57
MIPS unoptimized
•
ClockRate
5


ClockRate

6
.
37

10
1.57 106
CPI optimized  (1 (.43 / 2)  2  .21  2  .12  2  .24) /(1  .43 / 2)
ClockRate
5
MIPS optimized 

ClockRate

5
.
78

10
1.73 106
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