Transcript log 2 n ff - Auburn Engineering

A Random Access Scan Architecture
to Reduce Hardware Overhead
Anand S. Mudlapur
Vishwani D. Agrawal
Adit D. Singh
Dept. of Electrical Engineering
Auburn University, AL – 36849
USA
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Motivation for This Work
• Serial scan (SS) test sequence lengths and
power consumption are increasing rapidly.
– Reduction of test power and test time are
complimentary objectives in serial scan.
• Scope of increasing delay fault coverage is
limited in serial scan.
• In spite of the three advantages (test time,
power, and delay fault coverage) random
access scan (RAS) is not popular due to
high overhead.
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Outline
• Introduction
• Review of our “toggle” Flip-Flop design
• Highlight the uniqueness and feasibility
of our design due to the reduction of
two global signals
• Results on ISCAS Benchmark Circuits
• Conclusion
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Introduction
• Random Access Scan (RAS) offers a single
solution to the problems faced by serial scan (SS):
– Each RAS cell is uniquely addressable for read
and write.
– RAS reduces test application time and test power
which are otherwise complimentary objectives.
• Previous and current publications on RAS:
• Ando, COMPCON-80
• Wagner, COMPCON-83
• Ito, DAC-90
• Baik et al., VLSI Design-04, ITC-05, ATS-05, VLSI Design-06
• Mudlapur et al., VDAT-05
• Disadvantage: High routing overhead – test
control, address and scan-in signals must be
routed to all flip-flops.
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Contributions of Present Work
• Eliminate scan-in signal from circuit by
using a toggling RAS flip-flop.
• Eliminate routing of test control signal to
flip-flops.
• Provide a new scan-out architecture:
– A hierarchical scan-out bus
– An option of multi-cycle scan-out
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Serial Scan (SS)
PI
PO
Combinational Circuit
Scan-in
FF
FF
FF
Scan-out
Test control
(TC)
Example:
Consider a circuit with 5,000 FFs and 10,000
combinational test vectors
Total test cycles = 5,000 x 10,000 + 10,000 + 5,000
= 50,015,000
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Random Access Scan (RAS)
PI
PO
Combinational Circuit
Address
Inputs
FF
FF
FF
Scan-out
bus
Decoder
These signals
are eliminated
in our design
TC
During every test, only a subset of all Flip-flops needs to
be set and observed for targeted faults
Scan-in
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The “Toggle” RAS Flip-Flop
Combinational
Logic
1M
Combinational
Logic Data
U
0X
M
To Output
BUS
S
Clock
x
y
RAS-FF
√nff Lines
Row Decoder
Address (log2nff)
Output
BUS
Control
√nff Lines
Column
Decoder
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Toggle Flip-Flop Operation
Function
Clock
Normal Data
Toggle Data
Hold Data
Address decoder outputs
Row (x)
Column (y)
Active
0
0
Inactive
1
Active Clock
Inactive
Active Clock
1
Inactive
1
0
Inactive
0
1
Inactive
0
0
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Toggle Flip-Flop Operation (contd.)
Unaddressed FFs
RAS
FF
1
RAS
FF
01
Decoded
address
lines
RAS
FF
0
Addressed FF
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Macro Level Idea of Signals to RAS-FF
RAS
FF11
RAS
FF12
RAS
FF13
RAS
FF14
RAS
FF21
RAS
FF22
RAS
FF23
RAS
FF24
RAS
FF31
RAS
FF32
RAS
FF33
RAS
FF34
RAS
FF41
RAS
FF42
RAS
FF43
RAS
FF44
From 3
Other
RAS
Clusters
}
x1
4-to-1 Scan-out
Macrocell
x2
x3
x4
y1
y2
y3
y4
To Next
Level
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Scan-out Macrocell
• A 4x4 block scan-out data flow and control
logic
Data Bus From
4 RAS FFs
Control From
4 RAS FFs
{
To Next Level
Output BUS
Control Signal to
Next Level BUS
• Two D-FFs may be inserted at the outputs of
macrocell for multi-cycle scan-out.
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Routing of Decoder Signals in RAS
Address
(log2 √ nff)
Address
(log2 √ nff)
R
O
W
Flip-Flops
Placed on a
Grid Structure
D
E
C
O
D
E
R
COLUMN DECODER
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Gate Area Overhead
Gate area overhead of
=
Serial Scan
Gate area overhead of =
Random Access Scan
4n ff
n g 10n ff
6n ff  n ff
ng 10n ff
 100%
 100%
where nff – Number of Flip-Flops
ng – Number of Gates
Assumption: D-FF contains 10 logic gates.
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Gate Area Overhead (Examples)
1. A circuit with 100,000 gates and 5,000 FFs
Gate overhead of serial scan = 13.3 %
Gate overhead of RAS = 20.0 %
2. A circuit with 500,000 gates and 5,000 FFs
Gate overhead of serial scan = 3.6 %
Gate overhead of RAS = 5.5 %
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Overhead in Terms of Transistors
Gate area overhead of
=
Serial Scan
Gate area overhead of
=
Random Access Scan
10n ff
nt  28n ff
26n ff
nt  28n ff
 100%
 100%
Synthesis performed on SUN ULTRA 5 Machine
RAS has 16 transistors more than SS Flip-Flop
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Test Time
Test cycle reduction
600
400
200
Test clock cycles
(thousands)
800
0
s3271
s3384
s5378
s13207
Circuits
Scan
RAS
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Test Power
0.1
0.01
Test Power
(Normalized to
serial scan)
1
0.001
s3271
s3384 s5378
Circuits
Scan
s13207
RAS
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Case Study on an Industrial Circuit
•
•
A case study on an industry circuit was
performed at Texas Instruments India Pvt. Ltd.
The preliminary results were as follows:
1. The gate area overhead of RAS for a chip with
~5500 Flip-Flops and ~100,000 NAND equivalent
gates was of the order of 18 %
2. 75 % reduction in test time was observed. A speedup of up to 10X could be achieved using special
heuristics
3. An approximate estimate of the routing and area
overhead of RAS after physical layout was
estimated as 10.4 %
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Conclusion
• New design of a “Toggle” Flip-Flop reduces
the RAS routing overhead.
• Proposed RAS architecture with new FF has
several other advantages:
– Algorithmic minimization reduces test cycles
by 60%.
– Power dissipation during test is reduced by
99%.
• A novel RAS scan-out method presented.
• For details on “Toggle” Flip-Flop, see
Mudlapur et al., VDAT-05.
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