Transcript VDAT `05 Bangalore, 10-13, 2005

A Novel Random Access Scan
Flip-Flop Design
Anand S. Mudlapur
Vishwani D. Agrawal (Speaker)
Adit D. Singh
Department of Electrical and
Computer Engineering
Auburn University, AL 36849, USA
Ninth VLSI Design and Test Symposium – VDAT ’05
Bangalore, 10-13, 2005
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Motivation for This Work
• Conventional serial scan (SS) test sequences
are increasing rapidly to an unimaginable
quantity leading to long test time.
• Scan-in and scan-out result in high
switching activity during test.
• Reduction of power and test time are
complimentary objectives in serial scan.
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Outline
• Introduction
• The RAS solution and a unique “toggle”
Flip-Flop design
• Advantage of our design in eliminating
two global signals
• Results on ISCAS Benchmark Circuits
• Conclusion
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Introduction
• Random Access Scan (RAS) offers a single
solution to the problems faced by serial scan (SS):
– Each RAS cell is uniquely addressable for read or
write.
– RAS reduces test application time and test power
which are otherwise complimentary objectives.
• Publications on RAS:
• Ando, COMPCON-80
• Wagner, COMPCON-83
• Baik et al., VLSI Design-04
• Mudlapur et al., ITC-05
• Disadvantage: High routing overhead – test
control, address and scan-in signals must be
routed to all flip-flops.
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Serial Scan (SS)
PI
PO
Combinational Circuit
Scan-in
FF
FF
FF
Scan-out
Test control
(TC)
Example:
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Consider a circuit with 5,000 FFs and 10,000
combinational test vectors
Total test cycles = 5,000 x 10,000 + 10,000 + 5,000
= 50,015,000
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Random Access Scan (RAS)
PI
PO
Combinational Circuit
Address
Inputs
FF
FF
FF
Scan-out
bus
Decoder
These signals
are eliminated
in our design
TC
During every test, only a subset of all Flip-flops needs to
be set and observed for targeted faults
Scan-in
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The “Toggle” RAS Flip-Flop
Combinational Logic
Data
M
U
X
To Combinational
Logic
M
S
To Scan-out Bus
Clock
x
y
RAS-FF
√nff Lines
Row Decoder
√nff Lines
Column Decoder
Decoded address
lines
Address (log2nff)
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Toggle Flip-Flop Operation
Function
Clock
Normal Data
Toggle Data
Hold Data
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Address decoder outputs
Row (x)
Column (y)
Active
0
0
Inactive
1
Active Clock
Inactive
Active Clock
1
Inactive
1
0
Inactive
0
1
Inactive
0
0
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Toggle Flip-Flop Operation (contd.)
Unaddressed FFs
RAS
FF
1
RAS
FF
01
Decoded
address
lines
RAS
FF
0
Addressed FF
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Macro Level Idea of Signals to RAS-FF
RAS
FF11
RAS
FF12
RAS
FF13
RAS
FF14
x1
D-FF
D-FF
RAS
FF21
RAS
FF22
RAS
FF23
RAS
FF24
x2
D-FF
D-FF
RAS
FF31
RAS
FF32
RAS
FF33
RAS
FF34
x3
To
Next
Level
D-FF
D-FF
RAS
FF41
RAS
FF42
RAS
FF43
RAS
FF44
x4
y1
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y2
y3
y4
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D-FF
D-FF
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Gate Area Overhead
Gate area overhead of
=
Serial Scan
Gate area overhead of =
Random Access Scan
4n ff
ng 10n ff
6n ff  n ff
ng 10n ff
 100%
 100%
nff – Number of Flip-Flops
ng – Number of Gates
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Gate Area Overhead (Example)
A circuit with 5,120 gates and 512 FFs
Gate overhead of serial scan = 20 %
Gate overhead of RAS = 30.2 %
A circuit with 20,480 gates and 512 FFs
Gate overhead of serial scan = 8 %
Gate overhead of RAS = 12 %
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Overhead in terms of Transistors
Gate area overhead of
=
Serial Scan
Gate area overhead of
=
Random Access Scan
10n ff
nt  28n ff
26n ff
nt  28n ff
 100%
 100%
Synthesis performed on SUN ULTRA 5 Machine
RAS has 16 transistors more than SS Flip-Flop
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Results
Test vector reduction
600
400
200
Vectors (thousands)
800
0
s3271
s3384
s5378
s13207
Circuits
Scan
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RAS
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Results (Contd.)
Test power reduction
10
1
Normalized
power (LOG
scale)
100
0.1
s3271
s3384 s5378
Circuits
Scan
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s13207
RAS
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Conclusion
• New design of a “Toggle” Flip-Flop
reduces the RAS routing overhead.
• A proposed RAS architecture with new
FF has several other advantages:
– Algorithmic minimization reduces test
cycles by 60%.
– Power dissipation during test is reduced
by 99%.
• For details, see Mudlapur et al., ITC-05.
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