Transcript SeminarESE_xavix

Hybrid Pixel Readout Architectures
at the pixel ASIC level
Xavier Llopart
Tuomas Poikela
PH-ESE Seminar 8th May 2012
Outline
• Introduction
– A Pixel Chip
– Pixel Operation Modes
– Technology scaling
• Hybrid pixel chips:
–
–
–
–
–
Imaging
HEP low rate
HEP Triggered
HEP trigger less (Tuomas)
Dosimetry
• Conclusions
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PH-ESE Seminar 8th May 2012
2
A “typical” Pixel Chip
• Building blocks:
– Pixel Array:
• Array of NxM pixels
• Square or rectangular pixels
• Single pixel columns or multiple pixel columns (2,4…)
– End Of Column:
• Used as interface between the pixel array and the
periphery
– Analog → Test Pulse, pixel biasing, ….
– Digital → FIFO, TDC, logic…
– Slow Control (command decoder, IO logic…)
• Interface between the readout system (or module
controller) and the chip
– Analog Periphery:
• DACs, ADCs, BandGap, Efuses, Temperature
sensors,….
– Output Block:
• Serializers (PLL), High-speed-links, LVDS
End Of Column
Analog
Periphery
Slow Control
Output Block
IO PADs + Power
– IO PADs + Power:
• IO: CMOS, LVDS, CML, GTL…
• Power and Ground
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3
Pixel Operation Modes
• In a hybrid pixel detector the energy threshold is used to
eliminate noise or low energy events → Noise-free system
• Nature of measurements after discriminator:
– Particle Counting (PC)
• Count of number of events in a fix time (Shutter)
Threshold
– Time-Over-Threshold (TOT)
• TOT charge per event
• iTOT integral of the charge over a fix time (Shutter)
– Time of Arrival (TOA)
TOT
• Measure of the arrival time (Time stamping)
TOA
– Binary (Bi)
• 1 bit per event tagged with Bx
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4
Pixel readout architectures
•
Data type:
– Full frame:
•
All pixels are readout
– Zero-compressed:
•
•
Only pixels with valid events are fully readout
Other pixels are compressed (1-bit header)
– Zero-suppressed:
•
•
Only pixels with valid events are readout
Start readout type:
– Data driven→ Pixels start a readout as soon as a valid hit is acquired
– External driven → Readout is started externally
•
Acquisition type:
– Non-continuous → No particle detection while chip is readout (dead time)
– Continuous → Particle detection also while chip is readout
– Semi-Continuous → Some part of the pixel array doesn’t detect particles during readout
•
Triggered readout:
– Data is readout if matches some event information (Trigger)
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PH-ESE Seminar 8th May 2012
5
Hybrid pixel ASICs classification
Pixel Size Pixel
[um]
Array
Pixel Operation
Bits/Pixel
Data
Type
256*256
PC
14
Full frame
External
Noncontinuous
No
75
256*256
PC
4, 8 or 12
Full frame
External
Continuous
No
2012
55
256*256
PC
1,6,12 or 24
Full frame
External
Continuous
No
2006
55
256*256
PC, TOT or TOA
14
Full frame
External
Noncontinuous
No
35-40
384*384
512*512
TOA and TOT
PC and iTOT
24-32
0-compressed External
Continuous
No
25
64*64
TOT and TOA
9
0-compressed External
NonContinuous
No
2001
50*425
256*32
TOA and Binary
2 FIFO of 8 bit BCO 0-compressed External
Continuous
Yes
2005
100*150
52*80
Analog
?
0-suppresed
External
Continuous
0-suppresed
External
Continuous
Yes
External
Continuous
Yes
Continuous
No
Continuous
No
Chip Name
Technology
Year
Medipix2
IBM 250n
2005
55
EIGER
UMC 250nm
~2009
Medipix3RX
IBM 130n
Timepix
IBM 250n
SmallPix
IBM 130n
ClicPix_demo
TSMC 65nm
Alice1LHCb
IBM 250n
PSI46 (CMS)
IBM 250n
2012
(Q4)
2012
(Q4)
Start Acquisition Trigger
readout
Type
Readout
Yes
FEI3 (ATLAS)
IBM 250n
2006
50 *400
160*18
TOA and TOT
8-bit TOA +
address
EOC event
Buffering
FEI4 (ATLAS)
IBM 130n
2011
50*250
336*80
TOA and TOT
?
0-suppresed
TDCpix (NA62)
IBM 130n
2012
300
45*40
TOA and TOT
48
0-suppresed
ToPIX (PANDA)
IBM 130n
2012
100
116*110
TOA and TOT
48
0-suppresed
Timepix3
IBM 130n
2012
55
256*256
37
0-suppresed
Data
driven
Continuous
No
VeloPix
IBM 130n
2013
55
256*256
36
0-suppresed
Data
driven
Continuous
No
220
16*16
External
SemiContinuous
No
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Dosepix
IBM 130n
2010
PC and iTOT
TOA and TOT
TOA
PC
TOA and TOT
PH-ESE Seminar 8th May 2012
TOT
256
Full frame
Data
driven
Data
driven
Output data port
1-LVDS
@ 180 Mbps
32-bit CMOS DDR
@ 200 Mbps
1,2,4 or 8-LVDS
@ 250 Mbps
32-bit CMOS
@ 100 Mbps
1,2,4 or 8-LVDS
@ 250 Mbps
1 or 2-LVDS
@ 640 Mbps
32-GTL
@ 40 Mbps
6-8 bit analog
@ 40 MHz
1-LVDS
@ 40 Mbps
1-LVDS
@ 320 Mbps
4 CML
@ 3.2 Gbps
1-LVDS
@ 312.4 Mbps
1,2,4 or 8-LVDS DDR
@ 640 Mbps
4 CML
@ 4.8 Gbps
6
1-CMOS
@ 10 Mbps
Readout efficiency vs architecture
0.1
Simulation setup:
–
–
–
–
–
256x256 pixel array
32 bits/pixel
1 event → 1 pixel hit (no clusters)
Random position in pixel matrix
Readout clock = 100 MHz
•
Full frame → 32x256x256 bits
•
Full frame binary →1x256x256 bits
0.01
Chip readout Time [s]
•
3
110
4
110
•
0-suppresed → (32+8+8)*#_Hits
•
0-compressed :
–
–
–
0-suppressed readout
Full Frame Readout
0-compressed with column skipping
Full frame Binary readout
Pixels with valid events: (32 + 1)*#_Hits
Pixels with invalid events: 1*(#_noHits)
Column skipping: Columns with no valid
hits are not readout
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5
110
0.1
1
10
100
Occupancy [%]
Occupancy
Most efficient readout architecture
<2% [HEP]
0-suppressed
>2%
Full frame binary
>6% and <85%
0-compressed
>85%
[imaging]
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2012
Full frame readout
7
Technology scaling in HEP
16 µm
E_dff
cmos6sf25CoreLib
250nm
DFF_skt
Medipix2_lib
250nm
x 12
DFF_A
cmos8rf
130nm
x 18.3
DFF_A_XL
cern_cmos8rf_hd
130nm
x 39.2
DFQD1
tcbn65lp
65nm
x 77.2
33 µm
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8
What about digital Power?
• With technology scaling static and dynamic power density increases
• Use of low power (high-Vt) standard cells library helps to reduce the static
power consumption:
– Compared to a low-Vt process the reduction can be significant (x20) at medium-high
temperatures (>70C)
• Need to think in architectures that minimizes dynamic power
consumption:
–
–
–
–
–
Out-of-phase column to column clock (Medipix family, SmallPix, ClicPix…)
Clock gating → Pixel synchronous logic only enabled when a Hit is present (Timepix)
Asynchronous logic for Hit processing (Medipix family)
Allow a manageable clock skew along the column (2ns for FEI4)
Decrease of the digital pixel power supply → Instead of fast logic
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PH-ESE Seminar 8th May 2012
9
IMAGING
Imaging pixel chips requirements
•
High pixel rate
–
•
Due to high pixel rate, measurement in photon counting mode using a counter in the pixel counter
–
–
•
•
1 event → 1 count
Up to 24 bits (Medipix3RX) → >16*106 events
Full frame readout
Non-Continuous or continuous acquisition
–
•
Up to > 2 MHz/pixel (Eiger) → 35*109 event/s/cm2
Imaging synchrotron applications require continuous acquisition
Small square pixels
–
Higher spatial resolution (Medipix family) → 55x55 μm
Qin
Shutter
DataOut
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Readout [#Pixels*PixelBits]
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Readout [#Pixels*PixelBits]
11
Mpix2MXR20 (2005) & Timepix (2006)
Previous Pixel
3-bit THL Adj
Shutter
Mask
THL
Mux
Disc
Mux
Input
DDL
CSA
Overflow
Control
Ctest
Testbit
14-bit
Shift
Register
Disc
Polarity
THH
Conf
8-bits PCR
Test Input
Clk_Read
3-bit THH Adj
Next Pixel
Digital
Analog
Previous Pixel
Ref_Clkb
Clk_Read
Mux
4 bits thr Adj
Mask
Mux
Input
CSA
Disc
Shutter
THR
Ctest
Testbit
P0
P1
Polarity
Timepix
Shutter_int
Synchronization
Logic
14 bits
Shift
Register
Conf
8-bits PCR
Test Input
OvControl
Ref_Clk
Analog [email protected] Digital
Clk_Read
Next Pixel
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14080 m (pixel array)
3584-bit Pixel Column-255
3584-bit Pixel Column-1
3584-bit Pixel Column-0
16120 m
Timepix/Medipix2 chip architecture
Main Specs:
• 256x256 55µm square pixels
• Analog Power -> 440mW
• Bits stored in pixel → 14
• Serial readout (@100Mbps) → 9.17 ms
• Parallel readout (@100Mbps) → 287 µs
• Full custom design
• > 36M Transistors
Dynamic power is mitigated because:
• EoC is a serializer (FSR)
–
256-to-1 in serial readout
•
–
256-to-32 in parallel readout
•
•
256-bit Fast Shift Register
LVDS
IO
In
Logic
LVDS
32-bit CMOS Output
14111 m
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Out
Pixel Matrix frequency clock / 8
Out-of-phase column clock
–
Bandgap + 13 DACs
Pixel Matrix frequency clock / 256
–
Max readout clock frequency (parallel
readout) at pixel matrix is 12.5 MHz for a 3.2
Gbps chip readout
Column clock tree made by one buffer in the
EoC
PH-ESE Seminar 8th May 2012
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Continuous Readout architectures
[No Dead Time]
• The EIGER chip and Medipix3RX have continuous readout architectures
– EIGER stores the 12-bit counter into a on pixel storage capacitor (~3 µs to switch)
•
•
11 KHz @ 8 bit mode
22 KHz @ 4 bit mode
– Medipix3RX uses 2 x 12-bit programmable counter
•
•
•
•
2 KHz @ 12 bit mode
4 KHz @ 6 bit mode
24 KHz @ 1 bit mode
At transitions pixel logic assigns the logic to only one subframe
Qin
Shutter
CounterSel
DataOut
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Counter0
Counter1
Counter0
Counter1
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Counter0
Counter1
Counter0
Counter1
14
EIGER readout architecture
Token In
Sc0
0-7
Sc32
247 - 255
Super columns, 32 bit buses
•
Row 0
•
•
•
•
•
•
•
Super column structure
– 8 columns/super column
– 32 super columns
– Current mode data buses
Token Shift Register
– Connects 4 bits of the counter
storage cells or trimbits of a row
to the bottom register
Bus receivers
Perform I/V conversion
Multipurpose register
Configurable serial/parellel I/O
Super serializers
– Serialize data sent to the pad
32 Data pads
– 100 MHz DDR,TWELL
• Full custom design
Row/
Counter bits
Bus receivers
IO Pads
Serial OUT
Multipurpose Register
Serial IN
Super
Serializer
Super
Serializer
Data <0>
Data <1>
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Super
Serializer
Data <31>
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The EIGER pixel, digital part
Trim 0
Global
Threshold
setting
6 Threshold Trimbits
Trim 5
6
12 bit counter
(with buffered storage)
Bit 0
Shaper out
Discriminator
Overflow
Enable
Bit 11
Overflow
Reset
Counter Mode
(4,8,12 bits) Store
Trimbit ins/
Counter Outs
Pixel output stage
STORE (starved)
Counter
bit
Pixel counter
12 bits, binary, double buffered (cont.
readout), configurable (4,8,12 bit mode)
Threshold adj.
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6 bit DAC/pixel
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ROWSEL
COLUMN
DATA BUS
16
Medipix3RX readout architecture
EoC serializes/ data from pixel array:
•
•
Maximum column readout clock frequency < 8MHz
@ 2 Gbps
Out-of-phase column clock
Simple Clock tree in the pixel array
12-bit → 3072-bit
6-bit → 1536-bit
12-bit → 256-bit
–
12-bit → 3072-bit
6-bit → 1536-bit
12-bit → 256-bit
•
CounterL
CounterH
Column255
Column1
Column1
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TpC 255
TpC 254
EoC 255
TpC 253
10 LVDS out
17
ClkOut
EnableOut
DataOut[7]
DataOut[6]
DataOut[5]
DataOut[4]
DataOut[3]
DataOut[2]
DataOut[1]
DataOut[0]
DAC_OUT
DAC_OUT
EXT_DACIn
EXT_BGIn
EXT_BGIn
EXT_DACIn
VDD-Efuse
3.3V
VDDA33
Digital IO
2.5V
DVDD
DVSS
Digital Core
1.5V
VDD
GND
Analog Core
1.5V
VDDA
GNDA
TP_Switch
EoC 254
EoC 253
TpC 2
EoC 2
TpC 1
8 LVDS in
MatrixFastClear
Full digital verification up to 350 MHz
BandGap
Biasing
27 DACs (226 bits)
E-Fuses (32 bits)
Shutter
•
Pixel: cern_cmos8rf_hd library → LP and HD
Periphery: cmos8rf → Rvt and faster cells
DataIn
–
–
IO
Logic
CounterSelCRW
Use of standard cell libraries:
EoC 1
•
Reset
Continuous readout @ 1,6 or 12 bit
TpC 0
•
EnableIn
Regions of interest can be readout
ClkIn
•
EoC 0
Column0
Medipix3RX Pixel Schematic
Shutter
ConfigDiscL[0:4]
Event-by-event charge summing and allocation
–
–
–
–
ConfigDiscH[0:4]
gm
CTEST
Polarity
CSM_SPM
ColourMode
TestBit
TH[1]
Operation Mode
Readout mode
0
1
0
1
0
1
0
1
SPM, FP
SPM, FP
CSM, FP
CSM, FP
SPM, SPECT
SPM, SPECT
CSM, SPECT
CSM, SPECT
SRW
CRW
SRW
CRW
SRW
CRW
SRW
CRW
PH-ESE Seminar 8th May 2012
1
1
DataOutL
DataOutH
MaskBit
110 μm
0
0
1
1
0
0
1
1
COUNTERH
DISCH
Disc_CSM_SPM
CRW_SRW
CSM_SPM
ColourMode
Equalization
0
0
0
0
1
1
1
1
1
1
TestPulse
Multiple operation modes:
COUNTERL
PULSE
PROCESSING
LOGIC
1
GainMode[0:1]
2x 1, 6 or 12 bits
1x 24 bit
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1
DISCL
5
Preamp with 4 different gain modes
Pixel counter depth configurable:
–
–
•
Analog → charge summing
Digital → hit allocation
1
TH[0]
-Av
Continuous RW
•
•
CF
Inter-pixel communication:
CSM_SPM
•
5
DataInH
1
Fine Pitch (FP) → 55x55 (2 thresholds)
Spectrometry (SPECT)→ 110x110 (8 thresholds)
ColourMode
•
DataInL
1
18
HEP LOW RATE
HEP Low Rate pixel chips requirements
• Low Rate or sparse BX (ILC/CLIC)
– Non-continuous acquisition
• Detailed measurement of each event:
– Energy (TOT, ADC,…) → Used to reconstruct with high accuracy hit position
– Time (internal TDC or external trigger)
• Very small pixels (1 event stored / pixel)
– ClicPix_demo 25x25 μm [8 bits]
– SmallPix 40x40 μm [32 bits]
– Timepix 55x55 μm [14 bits]
• Avoid event pile-up → Low occupancy or fast readout
• Full frame readout (Timepix) or zero compressed readout architecture
(SmallPix and ClicPix)
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Zero-compressed readout architecture
To the pixel above
• Hit-Flag (HF) indicates if a pixel
contains a valid hit
Clk
– If HF pixel is readout
– If !HF pixel is skipped (1bit)
• Shifting based readout → Dynamic
power minimized
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4 bits TOT
Enable
logic
4 bits TOA
Analog
Frontend
Clock
divider
4 bits tuning DAC
• Each column is readout at full
speed clock (320 MHz) no
serialization possible at EOC →
careful digital design
Compression
logic
Mask, TP
• At the EOC the amount of pixels
hit have to be reconstructed
Disc_out
Data
Data
HF
Analog_bias Readout
Poweroff Load_conf Shutter
Clk
Data
To the pixel below
To the periphery
ClicPix_demo pixel schematic
21
Zero-compressed cluster architecture
•
•
•
•
•
Pixel clustering in 2x8 allows to further compress the data for low occupancies
It also reduces the area because some of the electronics can be shared (clock
distribution tree, biasing lines)
Compression can be disabled with a configuration command
Column skipping (using the same principle) can also be implemented
Being digitally verified for the 65nm process (HvT 0.9V SS 125C) @ 320MHz
0.1
Chip readout Time [s]
0.01
110
110
HF
4
0-suppressed readout
Full Frame Readout
0-compressed with column skipping
Full frame Binary readout
0-compressed 2x8 cluster with column skipping
Pixel Hit Flags
110
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3
5
0.1
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10
Occupancy [%]
22
100
HEP TRIGGERED
Triggered pixel chips requirements
•
Used in environments with very high Hit Rates:
–
•
Target hit rate for FEI4 is 400 MHz/cm2
Limited IO bandwidth (mass, space, storage capacity…)
–
Trigger is used to readout only selected events
•
Zero-suppressed events keeps the output bandwidth low
•
Also full frame binary readout is also used (Alice1LHCb) → 0-compressed…
•
Requires memory and latency
–
–
Memory on the End of Column (FEI3, PSI46)
Memory on Pixel (FEI4, Alice1LHCb)
•
Token pass readout architecture “typically” used at the pixel column
•
Pixel column clock tree with low skew required → Significant dynamic power
•
Continuous acquisition
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FEI4 floorplan
•
•
Move the EOC memory towards the pixel
2x2 pixels is the regular array structure
– Pixel digital block synthesized using ARM
cells
•
•
On-Pixel digital correction for analog
timewalk
Only 0.25% of Hits send to EOC
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26
FE-I3 vs FE-I4 chip dimensions
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27
HEP TRIGGER LESS (TUOMAS)
Trigger less pixel chips requirements
•
•
All events over threshold (valid events) are readout
Extremely high output bandwidth
–
–
–
–
–
•
•
VELOpix >12Gbps/chip
Data-Driven readout architectures
Zero-suppressed
Pixel clustering
Pixel/cluster memory
Continuous Acquisition
Pixel column clock tree required
Qin
Shutter
DataOut
End of Command
Address
Payload (TOT, TOA, Bi)
Data Packet
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29
DOSIMETRY
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30
Pixel in Dosimetry Mode
• Massive use of standard cell libraries at pixel level → “µ-DSP”
•
Very low output bandwidth
– Events are binned in energy in every pixel in a event-by-event operation mode
•
•
•
Low power architecture
Semi-Continuous acquisition → Rolling shutter
High programmability
220 µm
1
2
3
4
Future work
•
With TSVs, once they become reliable, will have an incredible impact in the design of future pixel
chips:
–
–
–
–
Floorplan → Column and Row readout
Redistribution layer between the sensor and the ASIC to allow full coverage
How do we probe test such a chip?
Bump-bonding process (handling)
TSVs
End Of Column
Analog
Periphery
Slow Control
Output Block
Output Block
Slow Control
Analog
Periphery
IO PADs + Power
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32
Conclusions
•
HEP Pixel ASICs are quickly evolving thanks to the semiconductor technology
scaling (x80 from 250nm to 65nm for a rad-hard design)
– SEU?
•
Digital designs are getting closer to the pixel front-ends and incredibly complex:
– Medipix3RX → inter-pixel communication to allow charge summing (analog) and hit allocation
(digital)
– FEI4 → Timewalk compensation based on TOT
– ClicPix → 0-compressed architecture
– DosePix → µ-DSP on pixel
•
Full digital verifications are a fundamental part of the design
•
With higher transistor density, digital static and dynamic power will be a big issue
– Power-efficient architectures must be used if possible
– The use of low power library is highly recommended
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33
Thanks
PH-ESE Seminar 8th May 2012
spare
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35
er
ut
End of Command
Address
Payload (TOT, TOA, Bi)
Data Packet
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36
tter
in
0xA
256bit
Start of Command (4+256 bits)
48bit 48bit 48bit 48bit 48bit
Out
0xA
Address[16bit]
TOA[14+4 bits]
Data Packet (48 bits)
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TOT[10bits]
0x7
0x1
0x
End of Comm
37
tter
Out
[#Pixels_Hit*Pixel
Bits]
[#Pixels_Hit*Pixel
Bits]
tter
nterSel
Out
Counter0
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Counter1
Counter0
Counter1
Counter0
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Counter1
Counter0
Counter1
38
Medipix3.0 (2009)
Medipix3RX (2011) using SC_130nm_XL
110 μm
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110 μm
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FEI4 Region schematic
• A 2x2-pixel unit with these functionalities:
•
•
•
•
Time-Stamping (up to 5 stored at a time)
ToT coded on 4 bits: no hit, small hit, long hit, analog values
Neighbor bit
Small hit  Available to Neighbor Region
hit proc.: TS/sm/big/ToT
Token
disc. top left
disc. top right
Read & Trigger
5 ToT memory /pixel
disc. bot. left
Neighbor
disc. bot. right
L1T
Read
5 latency counter / region
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40