Transcript W_Snoeys_AIDA2020_calx

AIDA 2020
DESY, June 13-17, 2016
HVCMOS or CMOS MAPS
for ultra high granularity calorimeters
W. Snoeys, CERN
p-ALPIDE3 chip: 200 MeV p at PSI
Acknowledgements
 The workshop organizers
 G. Aglieri, G. Anelli, F. Anghinolfi, P. Aspell, R. Ballabriga, S. Bonacini,
M. Campbell, J. Christiansen, R. De Oliveira, F. Faccio, P. Farthouat,
D. Gajanana, E. Heijne, P. Jarron, J. Kaplon, K. Kloukinas, A. Kluge,
T. Kugathashan, X. Llopart, A. Marchioro, S. Michelis, P. Moreira, K. Wyllie, L.
Musa, P. Riedler, M. Mager, M. Keil, D. Kim, A. Dorokhov, A. Collu, C. Gao, H.
Hillemanns, S. Hristozkov, A. Junique, M. Kofarago, M. Keil, A. Lattuca, M. Lupi,
C. Marin Tobon, D. Marras, M. Mager, P. Martinengo, G. Mazza, H. Mugnier, L.
Musa, H. Pernegger, T. Pham, C. Riegel, J. Rousset, F. Reidt, P. Riedler, J. Van
Hoorne, and P. Yang
and other collegues from CERN and the ALICE ITS upgrade
 Other collegues who provided material for this presentation : A. Macchiolo, T.
Hemperek, N. Guerrini, I. Peric
[email protected]
2
CMOS Monolithic Active Pixel Sensors
 CMOS MAPS have changed the
imaging world, reaching:
 less than 1 e- noise
(cfr S. Kawahito, PIXEL 2012)
 > 100 Mpixels
 Wafer scale integration
 Wafer stacking
 …
 Silicon has become the standard in
HEP in tracking applications both
for sensor and readout
 What could MAPs do for HEP and
for a high granularity calorimeter ?
[email protected]
Backside Illuminated 8M Pixel
Stacked Imaging Sensor
S. Sugawa et al. Sony Corp.
ISSCC 2013
3
Requirements
(disclaimer: by a person coming from tracking)

Radiation tolerance HL-LHC 3 ab-1
 Ionizing radiation 5 Mgy
 Non-ionizing radiation (displacement damage) 1.5 1016 1MeVneq/cm2
 Circuit typically more sensitive to ionizing radiation, sensor to non-ionizing
radiation

Single particle hits instead of continuously collected signal in visible imaging
 100% efficiency or close (fill factor close to 1)
 Time stamping
 Full CMOS in-pixel desirable

Possible architecture for high granularity calorimeter
 Use a small pitch (10…20 micron) pixel matrix
 Divide sensitive area of a pixel matrix in areas of ~ 1x1 mm2
 Count number of hit pixels for each of these ~ 1x1 mm2 areas
 Important to have good estimates on the rates and occupancies
[email protected]
4
Radiation tolerance : MOS transistor
A
B
D
C
Now here
After N.S. Saks et al, IEEE TNS, Vol. NS-31 (1984) 1249
G. Anelli et al., IEEE TNS-46 (6) (1999) 1690
•
Intrinsic transistor has become more and more radiation tolerant due to thinner gate oxide
•
In LHC enclosed NMOS transistors and guard rings in 0.25 μm CMOS to avoid large leakage current
•
In deeper submicron enclosed geometry usually no longer necessary for leakage, but for small
dimensions parasitic effects dominate (see next page)
Single event effects:
•
Single Event Upset : triple redundancy with majority voting
•
Latch-up not observed so far in LHC, some observed on MAPs at STAR, need attention in the design
[email protected]
5
NMOS
NMOS
PMOS
F. Faccio
TWEPP 2015
Large
transistors
Min length
transistors
•
In this 65nm technology at very high doses, the short channel transistor, especially the PMOS
degrades significantly
•
Also observed: bias and technology dependencies ! => need extensive measurement campaigns
6
Radiation tolerance : sensor
A. Macchiolo, R. Nisius, N. Savic, S. Terzo, 10th Hiroshima Symposium, X’iang, China, 2015
See also N. Savic et al. 27th RD50 workshop, CERN, 2015
Can no longer exploit thick sensitive layers:
•
Need depletion and drift field to collect signal charge fast before it can be trapped, although this
“depletion” becomes relative for high fluences due to the large number of traps.
•
Need thin layer to contain power consumption from leakage current, and appropriate reset circuit
•
Significant progress on study of microscopic defects to explain macroscopic behavior
(see M. Moll’s presentation RD50)
[email protected]
7
Hybrid versus Monolithic
NWELL
DIODE
PWELL
NMOS
TRANSISTOR
PWELL
NWELL
DEEP PWELL
h
e
e
h
h
e
e
Epitaxial Layer P-
PMOS
TRANSISTOR
h
Substrate P++
Hybrid
Monolithic
•
Large majority of presently installed systems
•
Easier integration, lower cost
•
100 % fill factor easily obtained
•
•
Sensor and ASIC can be optimized separately
Promising not only for pixel detectors but
also for full trackers
•
Potentially better power-performance ratio
and strong impact on material budget
•
MAPS installed in STAR and adopted for
ALICE ITS upgrade
•
•
Sensor other materials
•
ASIC standard CMOS
Full sensor depletion allows
•
prompt charge collection and radiation tolerance
New technologies (Through-Silicon-Vias, microbumping, etc) could make distinction more vague. Stacked
CMOS imagers are available in industry, but usually not with per pixel connection. ATLAS & CLIC (I. Peric,
R. Ballabriga et al.) are investigating capacitive coupling between sensor and readout chip.
[email protected]
8
New ALICE ITS Layout
~24000 CMOS Pixel Sensors
10 m2 sensitive area
12.5 Gpixels
Outer Barrel
Inner Barrel
Radiation load
TID: 2.7 Mrad
NIEL: 1.7 × 1013 1 MeV neq/cm2
Technical Design Report for the Upgrade of the ALICE
Inner Tracking System
J. Phys. G 41 (2014) 087002
CERN-LHCC-2013-024 ; ALICE-TDR-017
Barrel geometry
3 Inner Barrel layers (IB) 0.3% X0
4 Outer Barrel layers (OB) 1% X0
FCC 2016 – [email protected]
Coverage
23 mm < r < 400 mm, |h| < 1.22
Layers z-lengths: 27 - 150 cm
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Technology for ALPIDE
Pixel Sensor CMOS 180 nm Imaging Process (TowerJazz)
SUB
SUB
PIX_IN
3 nm thin gate oxide, 6 metal layers
pwell
NWELL
DIODE
NMOS
TRANSISTOR
PMOS
TRANSISTOR
AVDD
IRESET
VRESET
IRESET
PIX_IN
A)
deep pwell
p+
n+
pwell
p+
p+
nwell
PWELL
deep pwell
NWELL
DEEP PWELL
h
Epitaxial Layer PSubstrate P++
Not to scale
Spacing
Spacing Diameter Spacing
C)
Diameter
B)
e
e
h
p+
p--
n+
+
epitaxial layer
p substrate
h
h
+
p-- epitaxial layer
Collection
electrode
p--
p substrate
VRESET_P
e
e
+
nwell
deep pwell
PWELL
p+
nwell VRESET_P
deepp pwell
p
n
Not to scale
PMOS Reset
M0b
p+
IRESET
Collection
electrode
AVSS
SUB
• High-resistivity (> 1kW cm) p-type epitaxial layer (18 mm to 30 mm) on p-type substrate
• Deep PWELL shielding NWELL allowing PMOS transistors (full CMOS within active area)
• 2 mm n-well diode, ~100 times smaller than pixel => low capacitance => large S/N
• Reverse bias applied to the substrate to increase the depletion volume around the
NWELL collection diode => further reduce capacitance and increase radiation tolerance
[email protected]
10
ALPIDE Chip Die picture
30 mm
Matrix 4.12 cm2
(512 × 1024 pixels)
Soldering pads
Analog DACs
512 x 26.88 um = 13.76 mm
15 mm
1024 x 29.24 um = 29941.76 um
Digital Periphery
1.208 mm
Regular Pads + Custom Blocks
[email protected]
11
ALPIDE Chip Floorplan
30 mm
Matrix 4.12 cm2
(512 × 1024 pixels)
Soldering pads
Analog DACs
512 x 26.88 um = 13.76 mm
15 mm
1024 x 29.24 um = 29941.76 um
Digital Periphery
1.208 mm
Regular Pads + Custom Blocks
[email protected]
12
ALPIDE Power Estimates
180.0
160.0
[mW]
140.0
152 mW
5.0
18.8
120.0
100.0
30.6
60.0
Other
DTU-LVDS
transmitter
18.5
71 mW
18.5
45.7
5.0
35.5
35.5
3.0
3.2
3.0
3.2
3.0
3.2
22.2
22.2
22.2
ALPIDE-4 Inner chip
[mW]
ALPIDE-4 Master
chip [mW]
ALPIDE-4 Slave chip
[mW]
40.0
20.0
Local Bus (1/7)
20.0
5.0
16.9
80.0
DCLK tx
157 mW
0.0
Sensitive area: 4.12 cm2
Inner Barrel: 36.9 mW/cm2
Outer Barrel: 20.2 mW/cm2
DTU-Serializer
DTU-PLL
Digital Periphery
Strobing
Pr. Encoders
Bias
In the matrix:
(analog + digital)/area
( 22.2 + 3.2 )/4.12
= 6.2 mW/cm2
Analog Pixels
With 40 nW front-end and Q/C ≈ 80 mV analog power
consumption still dominant within the matrix
Matrix readout only active if hit present
Clock gating in the digital periphery
For the future more work needed on Q/C, architecture
periphery and transmitter for overall power consumption
[email protected]
13
*NIM A 731 (2013) 125
Analog power ~ (Q/C)-2 *
… but Q will decrease as we need thin for radiation tolerance => work on capacitance
•
Transistor noise ≈ 0.16 mV at 40 MHz BW for 1 μA
(10 nA/100x100 μm2 pixel = 10 mW/cm2) … but pitch likely too large
4 fC 0.4 fC 0.04 fC
S
Q

 25   4mV 

N
C
1 pF 0.1 pF
10 fF
Collection depth
•
300 mm
30 mm
3 mm
Monolithic
Transistor noise ≈ 1.6 mV at 40 MHz BW for 10 nA
=> need Q/C = 40 mV for S/N=25
(10 nA/10x10 μm2 pixel = 10 mW/cm2)
• Conventional 300 mm thick strip detector: Q/C = 4fC/20pF = 0.2mV…
n+
-+
- +
- +
- +
-+
- +
- +
- +
- +
- +
- +
p=
- +
• ALPIDE Q/C ≈ 0.2 fC/2.5 fF = 80 mV distributed over a few pixels
• Digital signal if Q/C > 300 mV on a single pixel
V=
• Some help from non-linearity in weak inversion
[email protected]
14
Influence of Cdet
VDDA
20nA
IBIAS
0.5nA
M0
Csour ce
M7
ITHR
source
Cs
PIX_IN
IDB
M4
OUT_D
M1
VCASN
M5
VCASP
M6
M2
M8
M3
curfeed
OUT_A
COUT_A
ALPIDE front end – D. Kim et al. TWEPP 2015
Ccurfeed
GNDA
• Increased current in front end similar to the ALPIDE front end in first branch from 20 nA
to 200 nA (= 50 mW/cm2a for 28 μm ALPIDE pitch) and varied detector capacitance
between 0.25 fF, 2.5 fF and 25 fF.
• RESULTS see next slides
DISCLAIMER: no optimisation, purely schematic simulation, VERY preliminary
[email protected]
15
Influence of Cdet, Qin = 300 e-:
0.25fF
2.5fF
~ 300 mV
25fF
2 μs
[email protected]
Do not reach threshold with 25 fF...
16
Cdet also significantly influences speed:
0.25fF
~ 300 mV
2.5fF
25fF
25fF
2.5fF
0.25fF
10 ns
[email protected]
20 ns
Do not reach threshold with 25 fF...
17
Timewalk at Cdet of 2.5 fF, Qin=100 … 1000 e-:
10 ns
[email protected]
20 ns
18
Cdet of 2.5 fF, Qin=1000 … 10000 e-:
10 ns
[email protected]
20 ns
19
ALPIDE Pixel Layout Features
Pixel layout
Front End
Priority encoder
26.88 μm
Matrix
(detail)
Priority encoder
Collection
Diode
Digital Pixel
Section
9.66μm
19.58 μm
29.24 μm
Smaller in-pixel area desirable, will ease charge collection, allow smaller pixel pitch, etc
Could we reduce circuit area ?
• Front end contains large filtering capacitance, can it be reduced/eliminated ?
• Digital pixel section contain mask and test FF and 3 data memories
• Priority encoder needs replacement, counting probably simpler (and smaller)
20x20 μm2 looks feasible in this 180nm technology. Finer technology will increase NRE.
[email protected]
20
High Q/C yields DEVICE DESIGN challenge
uniform depletion layer with a small collection electrode
Collection
electrode
High energy
particle
Collection
electrode
High energy
particle
 A uniform depletion layer for uniform response and radiation tolerance: larger
pixels more difficult
 Optimal geometry and segmentation of the read-out electrode (minimum C)
 Effective charge resetting scheme robust over a large range of leakage currents
 Pattern density rules in very deep submicron technologies very restrictive.
 Insulation of the low-voltage transistors from the high voltage substrate.
Sensor needs to be designed in close contact with the foundry!
21
[email protected]
Q/C vs Full depletion
Junction on the front
CE
Pwell
Nwell
Deep Pwell
Pwell
Nwell
P-epitaxial layer
P-substrate
•
Deep pwell shields nwell from epi
•
AC coupling between CE and circuit allows
higher reverse bias (PEGASUS Bonn/IPHC)
•
Either simple in-pixel circuit or large
collection electrode for full depletion
•
ALICE 2.5 fF but no full depletion
Circuit inside collection electrode
Pwell
Nwell collection electrode
(ATLAS, CLIC, LePIX)
•
Depletion easier, risk of coupling into input
•
Keep in-pixel circuit simple for low C, or use
it as smart detector in hybrid solution
•
Difficult to go below 10 fF
P-substrate or P-substrate with epitaxial layer
Pwell
Nwell
Deep Pwell
N-epitaxial layer
P-substrate
[email protected]
Pwell
Nwell
Junction on the back or deeper into silicon
•
Full depletion with very small collection
electrode and potentially very low C
•
Example: Change epilayer type (RAL)
22
Circuit inside collection electrode
I. Peric KIT
-HV
AMS 350 nm HV process: sensor chips with
• Analog or digital coupling into FEI4
• Integrated digital readout
FEI4
3.3V
-
-
C3PD (Clicpix Capacitively Coupled Pixel Detector) in 180nm HV CMOS
Clicdp collaboration
CLICpix2
2nd version of CLICpix with larger matrix
65nm CMOS
128 x 128 pixels on 25mm pitch
5-bit ToT, 8-bit ToA, Power pulsing etc
C3PD
AMS 180nm HV-CMOS
Stand alone readout or compatible with
CLICpix2
http://dx.doi.org/10.1016/j.nima.2016.03.072
[email protected]
Circuit inside collection electrode
L-Foundry 150 nm process :
• deep N-well/P-well
• Up to 7 metal layers
• Resistivity of wafer: >2000 Ω·cm
• Small implant customization
• Backside processing
Collection with (edge-TCT)
I. Mandic, B. Hiti (Ljubljana)
CCPD_LF prototype:
• Pixel size: 33um x 125 um (6 pix =2 pix of FEI4)
• Chip size: 5 mm x 5 mm (24 x 114 pix)
• Bondable to FEI4
• 300um and 100um version
• Bonn + CCPM +KIT
Spectrum of 55Fe and 241Am after 1015neq/cm2
24
SiO2: XFAB 180nm : First results
Bonn
[email protected]
Collection with (edge-TCT) preliminary
1015neq/cm2
100 Ω·cm
Transistors threshold shift (TID)
Acceptor
removal
NMOS
700Mrad
PMOS
I. Mandic, B. Hiti (Ljubljana)
1 mA/cm2
Sensor reverse current
S. Fernandez-Pereza(CERN).
Spectrum of 55Fe and 90Sr before and after 5x1014neq/cm2
-450 V
25
ALPIDE Development for ALICE ITS Upgrade
Design team: G. Aglieri, C. Cavicchioli, Y. Degerli, C. Flouzat, D. Gajanana, C. Gao, F. Guilloux, S. Hristozkov, D. Kim, T.
Kugathasan, A. Lattuca, S. Lee, M. Lupi, D. Marras, C.A. Marin Tobon, G. Mazza, H. Mugnier, J. Rousset, G. Usai, A. Dorokhov,
H. Pham, P. Yang, W. Snoeys (Institutes: CERN, INFN, CCNU, YONSEI, NIKHEF, IRFU, IPHC) and comparable team for test
2013
pALPIDEss-0
20mm x 20mm and 30mm x 30mm pixels (analogue readout)
pixel geometry, starting material, sensitivity to radiation
Matrix with 64 columns x 512 rows
22 mm x 22 mm pixels
In-pixel discrimination and buffering
Zero suppression within pixel matrix
1.8 mm
Explorer
11 mm
1.8 mm
1.8 mm
2012
30mm
Full-scale prototype
pALPIDE-1
Apr-2015
pALPIDE-2
Oct-2015
pALPIDE-3
Jul-2016
ALPIDE
[email protected]
Pixel pitch: 28 mm x 28 mm, ~500 000 pixels
4 sectors with pixel variants
1 register/pixel, no final interface
15mm
2014
4 sectors with pixel variants
Optimization of circuits
Allowing integration in ITS modules
No high-speed serial output (1.2 Gbit/s replaced by 40 Mb/s)
8 sectors with pixels variants
All Final Functionalities and Features
Final production prototype (submission last week)
=> significant funding for submissions in the R&D phase.
26
Wafer-scale integration
Courtesy: N. Guerrini Rutherford Appleton Laboratory
Wafer-scale integration possible due to stitching
• Would ease assembly of large areas
• Has serious design implications
• One fab in a foundry: 1Mwafers/year, for ALICE (10 m2) 1.4 kwafers (200 mm), volume
capability ok even for significantly larger areas
[email protected]
27
Conclusions
Achieved on a 3 x 1.5 cm2 system-ready chip:
•
Sensitive area 4.12 cm2, granularity ~28x28 μm2, spatial resolution 5 μm
•
With 40 nW front-end and Q/C ≈ 80 mV, hit-driven matrix readout and clock gating in the digital
periphery, power consumption (mW/cm2):
matrix: analog 5.4 digital 0.78, overall inner: 36.9 and outer barrel: 20.2
Relevance for high granularity calorimeter:
• Promising but more work needed:
•
Need accurate information on rates and occupancies to establish and optimize requirements
•
Low C for low analog power and speed (C << 1fF ?)
•
Combine with full depletion for sensor radiation tolerance. Several promising developments.
•
Thin sensitive layer (18-30 μm) to contain sensor leakage
•
Transistors radiation tolerance: relevant for all architectures: need measurement to larger
doses, bias dependent effects require more extensive verification and more robust design
•
No clock distribution over the matrix, counting easier than full tracking
• Wafer scale integration (stitching)
to ease assembly of larger areas
[email protected]
28
Backup
29
NOT SO LONG AGO… (0.5 μm)
1.E-01
N-ch Standard W/L=10/0.5
Id [A]
1.E-04
Prerad
1.E-07
After 2Mrad
1.E-10
1.E-13
-0.40
0.40
1.20 2.00
Vg [V]
2.80
 Vt-shift
 Weak inversion slope change
 NMOS transistor leakage
[email protected]
30
ENCLOSED LAYOUT
1.E-01
1.E-03
1.E-05
Id [A]
1.E-07
1.E-09
Prerad
1.E-11
After 2Mrad
1.E-13
-0.40
[email protected]
0.40
1.20
2.00
Vg [V]
2.80
31
ITS Chip General Requirements
Parameter
Inner Barrel
Chip size (mm x mm)
Outer Barrel
15 x 30
Chip thickness (mm)
50
100
Spatial resolution (mm)
5
10 (5)
Detection efficiency
Fake hit rate
> 99%
< 10-5 evt-1 pixel-1 (ALPIDE << 10-5)
Integration time (ms)
Power density (mW/cm2)
TID radiation hardness (krad) (**)
NIEL radiation hardness (1 MeV neq/cm2) (**)
< 30
< 300 (~35)
< 100 (~20)
2700
100
1.7 x 1013
1.7 x 1012
Readout rate, Pb-Pb interactions (kHz)
Hit Density, Pb-Pb interactions (cm-2)
(< 10)
100
18.6
2.8
(*) In
color: ALPIDE performance figure where above requirements
(**) 10x radiation load integrated over approved program (~ 6 years of operation)
[email protected]
32
Pixel
Cdet~2.5 fF @ -6 Vbb
Cin~1.6 fF
3 hit storage registers (MEB)
v
PIX_IN
v
tf~= 10 ns
5-10 ms
OUT_A
~2 ms peaking time
OUT_D
DV=Q/C
threshold
tr> 100 us
t
t
STROBE
Analog front-end and discriminator continuously active
Non-linear and operating in weak inversion. Ultra-low power: 40 nW/pixel
The front-end acts as analogue delay line
Test pulse charge injection circuitry
Global threshold for discrimination -> binary pulse OUT_D
Front End Characteristics
Gain (small signal) [mV/e]
ENC [e]
Threshold [e]
4
3.9
92 ± 2
Digital pixel circuitry with three hit storage registers (multi event buffer)
Global shutter (STROBE) latches the discriminated hits in next available register
In-Pixel masking logic
[email protected]
33
Matrix Readout
Pixels
512
Pixels
RESET
512
512
VALID
SELECT
10
RESET
Priority Encoder
512
ADDR
Priority Encoder
512
VALID
SELECT
Pixels
RESET
STATE
STATE
512
RESET
512
Pixels
STATE
STATE
512
511
10
ADDR
0
Periphery
Clock
Control
+ trigger
Data
The Priority Encoder sequentially provides the addresses of all hit pixels in a double
column
Combinatorial digital circuit steered by peripheral sequential circuits during readout of a frame
No free running clock over matrix. No activity if there are no hits
Energy per hit: Eh ~= 100 pJ -> ~3 mW for nominal occupancy and readout rate
Buffering and distribution of global signals (STROBE, MEMSEL, PIXEL RESET)
[email protected]
34
Analog Power Consumption:
Noise sources in a FET
EQUIVALENT WITH :
dvieq2
WHERE:
dieq2
dieq2 = gm2dveq2
In weak inversion (WI):
gm ~ I
dveq2 = (KF /(WLCox2fα)+ 2kTn/gm)df
In strong inversion (SI)
gm ~ √I
dveq2 = (KF /(WLCox2fα)+ 4kTγ/gm)df
Transconductance gm related to power consumption
[email protected]
35
Noise sources in a FET (2)
1.E-07
Prerad
After 100 Mrad
After 100 Mrad
After Annealing
After Annealing
Noise [V/Hz ]
Prerad
1/2
1/2
Noise [V/Hz ]
1.E-07
1.E-08
1.E-09
1.E+02
1.E+03
1.E+04
1.E+05
Frequency [Hz]
1.E+06
1.E+07
1.E+08
1.E-08
1.E-09
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
PMOS
NMOS
Note : Radiation tolerance (0.25 mm CMOS) !
Deeper submicron generally even more rad tolerant
[email protected]
1.E+08
Frequency [Hz]
36
Signal-to-noise, charge over input capacitance ratio
and
analog power consumption for MOS input transistor
or
For constant S/N:
Analog power is very strongly dependent on Q/C
Want SMALL electrode for low C
m = 2 for weak inversion up to 4 for strong inversion
[email protected]
37
pALPIDE-2 Test Beam Results
Detection Efficiency and Fake Hit Rate before and after irradiation
epi= 30 mm, spacing = 4 mm, VBB= -6V
Nominal threshold setting ITHR = 500 pA
edet > 99% @ lfake << 10-5 / event/pixel -> large margin over design requirements
Measurements on chips with 30 mm high-resistivity epitaxial layer, thinned to 50 mm,
-6 V reverse bias
1 non irradiated and 1 irradiated with 1.7 ·1013 1 MeV neq/cm2
[email protected]
38
Position Resolution: pALPIDE-2
epi= 25 mm, VBB=-6V, spacing= 2 mm
pALPIDE-2: sdet ≈ 5 mm is achieved before and after (1.0 x 1013) irradiation
Measurements on chips with 25 mm high-resistivity epitaxial layer, thinned to 50 mm,
Pixel pitch ~ 28 mm
Note: pixel height is comparable to pixel pitch, good for inclined tracks
[email protected]
39
Example of triplicated design
Gigabit Optical Link (GOL) for LHC
Designed @ CERN





0.8 and 1.60 Gb/s optical link
Unidirectional
< 300 mW
G-link and 8-10 bit protocol
TMR logic
[email protected]
40
Standard charge sensitive pulse processing front end
(no integration over a fixed time)
RESET
OTA
Charge Sensitive
Amplifier
H(s)
Pulse
Processing
Shaper
ENC: total integrated noise at the output of the pulse shaper with respect to
the output signal which would be produced by an input signal of 1 electron.
The units normally used are rms electrons.
RESET: switch or high valve resistive element
W. Snoeys – Legnaro, April 2013
41
ANALOG POWER
‘standard’ front end noise equations
2
ENCTOT
 ENCd2  ENC 2f  ENC02
where
Transconductance gm related to power consumption
thermal
4kTCt2
ENC 
. X ( n)
2
gmq  s
3
1
B( , n  )n 2 2 n
2 ( n! e )
X ( n)  2
4
n2n
1/fnoise
KFF Ct2
ENC  2
.Y (n)
2
CoxWL q
1 n!2 e 2 n
Y ( n) 
( 2n )
2n n
shot noise
2
d
2
f
ENCo2 
2qI o s
.Z (n)
2
q
1
1
B( , n  ) 2 2 n
2 ( n! e )
Z ( n)  2
4n
n 2n
Ref.: Z.Y. Chang and W.M.C. Sansen : ISBN 0-7923-9096-2, Kluwer Academic
Publishers, 1991
W. Snoeys – Legnaro, April 2013
42
Influence of shaper order n
n
1.00
2.00
3.00
4.00
5.00
6.00
7.00
X(n)
0.92
0.85
0.95
1.00
1.11
1.17
1.28
Y(n)
3.70
3.41
3.32
3.28
3.25
3.23
3.22
Z(n)
0.92
0.63
0.52
0.45
0.40
0.36
0.34
 Ref.: Z.Y. Chang and W.M.C. Sansen : ISBN 0-7923-9096-2, Kluwer
Academic Publishers, 1991
 Ref. 2 : V. Radeka “Low-noise techniques in detectors” Ann. Rev. Nucl.
Sci. 1988, 38, 217-77
 Ref. 3 : E. Nygard et al. NIM A 301 (1991) 506-516
W. Snoeys – Legnaro, April 2013
43
STITCHING FOR LARGER AREA CMOS SENSOR
In one dimension:
I/O and power pads
Guard ring
Peripheral circuitry
Active Area
15 cm
 Stitching is combining part of the reticle to obtain a chip with an area larger than
the reticle (done for large professional CCDs for instance)
 All connections to the exterior on one side
 All routing using on-chip metal layers
 All local functions integrated
[email protected]
What is a ‘digital signal’ ?
The Boltzmann tyranny
Log(Id)=f(Vg) (Logarithmic scale)
1.00E-01
1.00E-03
Exp(
Vgs
)
nkT/q
Ion
1.00E-05
1.00E-07
Strong
inversion
Weak
inversion
1.00E-09
1.00E-11
Ioff
1.00E-13
-0.40 0.05
0.50
0.95
1.40
1.85
2.30
Weak inversion slope: Ion/Ioff=104 => 300-400 mV
Need this on a single pixel !!
Maybe some day we can eliminate analog power consumption
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45