Transcript Summary of the last 3 months - Indico

Layout techniques for increased
radiation tolerance in commercial
CMOS for pixel readout circuits
W. Snoeys
Microelectronics Group, EP Division, CERN
Representing the ALICE pixel, LHCB RICH and RD49 collaborations
CERN EP Seminar
October 19, 1998
Walter SNOEYS - CERN - EP - MIC
Other contributors and
Acknowledgements
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Michael Campbell
Eugenio Cantatore
Ken Wyllie
Domenico Minervini
Roberto Dinapoli
Elena Pernigotti
Katelijn Vleugels
Pierre-Marie Signe
Federico Faccio
Etam Noah
Giovanni Anelli
Marco Delmastro
I. Ropotar
L. Casagrande
Bettina Mikulec
Milo Luptak
Peter Sonderegger
Carlos Lourenco
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Erik Heijne
Pierre Jarron
Alessandro Marchioro
Mike Letheren
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Willy Sansen
Franco Corsi
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Michael Burns
Michel Morel
Paolo Martinengo
Stefania Saladino
Fabio Formenti
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Franco Meddi et al.
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Wolfgang Klempt
Federico Antinori
Walter SNOEYS - CERN - EP - MIC
OVERVIEW
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Problem with total dose in standard CMOS
technologies
Principle and effectiveness of layout
techniques
Design description and electrical results on
pixel prototypes
Irradiation results on pixel prototype
Design implications
Conclusions and perspectives
Walter SNOEYS - CERN - EP - MIC
Total ionizing irradiation
dose problem in
commercial CMOS
Radiation induces
positive fixed oxide
charge and
interface states
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Vt - shift
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weak inversion
slope change
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mobility change
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LEAKAGE in
NMOS transistors
N-ch Standard W/L=10/0.5
Prerad
Id [A]
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After 2Mrad
1.E-01
1.E-04
1.E-07
1.E-10
1.E-13
-0.40 0.56 1.52 2.48
Vg [V]
Example from 0.5 mm technology
(tox ~ 10 nm)
Walter SNOEYS - CERN - EP - MIC
NMOS TRANSISTOR LEAKAGE
ENCLOSED TRANSISTOR LAYOUT
Prerad
After 2Mrad
Gate
Drain
Id [A]
Well
1.E-01
1.E-04
1.E-07
1.E-10
1.E-13
-0.40 0.50 1.40 2.30 3.20
Vg [V]
Source
Example from 0.5 mm technology
(tox ~ 10 nm)
Walter SNOEYS - CERN - EP - MIC
NMOS INTER-TRANSISTOR
LEAKAGE
Well/
Substrate
Drain1
Source1
Gate1
P+
Source2
Foxfet current [A]
GUARD RINGS
1.E-02
1.E-04
1.E-06
1.E-08
1.E-10
1.E-12
Gate2
0
N+
1000
2000
Total Dose [krad(SiO2)]
poly gate
guardring
no gate
Walter SNOEYS - CERN - EP - MIC
Transistor Threshold shift
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Tunneling of
trapped charge
in thin oxides
DVT ~ 1/tox2 for
tox > 10nm
DVT ~
for
tox < 10 nm
A
B
1/tox3
D
C
After N.S. Saks, M.G. Ancona, and J.A. Modolo,
IEEE Trans.Nucl.Sci., Vol. NS-31 (1984) 1249
Walter SNOEYS - CERN - EP - MIC
Layout Techniques for
Radiation Tolerance :
Conclusion
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N-channel transistor leakage solved by
enclosed geometry layout
N-channel inter-transistor (field) leakage
solved by guard rings
Radiation induced trapped charge and
interface :
- reduced for thin oxides
- for very thin oxides (tox < 10 nm)
reduced much more
=> radiation induced transistor parameter
shifts smaller and smaller in deeper
submicron technologies
Walter SNOEYS - CERN - EP - MIC
A Pixel Readout Prototype in
Radiation Tolerant Layout
shaper
Rfb
comparator
Cfb
delay
logic
preamp
Cin
test
analog test FF
input
data
FF
threshold Clk strobe
&
setting
polarity
leakage current
compensation
mask
FF
Leakage current compensation after F. Krummenacher, Nucl. Instr. and
Meth., Vol. A305 (1991) 527-532, modified to accommodate both positive
and negative detector leakage current
Walter SNOEYS - CERN - EP - MIC
Counts (pro mille)
ALICE1 ELECTRICAL RESULTS
Detector leakage current
compensation
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No pixel threshold
change
Noise increases with
detector leakage
current as expected
1200
1000
800
600
400
200
0
10
30
50
70
Input (mV) (uncal. thresh. ~
Ileak = 1.4 nA,
2100
noise
el.) ~ 180 e rms
Ileak = 16 nA, noise ~ 210 e rms
Ileak = 100 nA, noise ~ 330 e rms
Walter SNOEYS - CERN - EP - MIC
Added delay (ns)
LHC2TEST/ALICE1TEST
ELECTRICAL RESULTS
Timewalk
threshold =
1650 el.
threshold =
2000 el.
threshold =
6400 el.
140
120
100
80
60
40
20
0
0
5000
10000 15000 20000 25000
Input charge (electrons, uncalib.)
Walter SNOEYS - CERN - EP - MIC
Added delay (ns)
ELECTRICAL RESULTS
Timewalk on LHC1 for comparison
150
100
50
0
0
5000
10000 15000 20000 25000
Input charge (el)
Walter SNOEYS - CERN - EP - MIC
A Pixel Readout Prototype in
Radiation Tolerant Layout :
Summary Electrical Results
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for a detector leakage current increase of 1
to 200nA :
- threshold variation ~ 1%
- noise increase from about 200e RMS to
400e RMS for holes, and to 350e RMS
for electrons.
threshold variable between 2000 to 15000
holes or electrons
threshold spread too large (400 - 500 e
RMS)
timewalk within 25 ns for only a few 100
electrons above threshold
Walter SNOEYS - CERN - EP - MIC
ALICE2TEST ELECTRICAL RESULTS
Threshold uniformity and noise
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Threshold variation
about 160 e rms,
without 3 bit
threshold adjust
Noise about 220 e
rms
1 mV ~ 100 e
Walter SNOEYS - CERN - EP - MIC
ALICE2TEST ELECTRICAL RESULTS
Average Threshold, Threshold
variation and average noise
Electrons
40000
20000
0
-20000
-40000
-400 -300 -200 -100
Threshold
0
100 200 300 400
Vth(mV)
Variation (rms)
Noise (rms)
Walter SNOEYS - CERN - EP - MIC
ALICE2TEST (0.25 mm) :
Summary Electrical Results
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Characterization in progress
Already established :
- minimum threshold 1500 e or below
- 3 bit threshold adjust works
- detector leakage current compensation works
up to several 100 nA/pixel
- both dynamic and static counter based delay
lines work
Walter SNOEYS - CERN - EP - MIC
LHC2TEST/ALICE1TEST
Evolution of Threshold and Threshold
Variation with Xray Dose
3000
electrons
2500
2000
1500
1000
500
0
0
500
1000
Dose (kRad)
Threshold
Threshold variation (rms)
Walter SNOEYS - CERN - EP - MIC
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Analog no
change
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Digital can be
explained by
Vt shift
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Validates
layout
approach on
global scale
I (mA)
LHC2TEST/ALICE1TEST
Evolution of Power Consumption
with Xray Dose
8
7
6
5
4
3
2
1
0
0 100 200 300 400 500 600 700 800
Dose (kRad)
Digital
Walter SNOEYS - CERN - EP - MIC
Analog
LHC2TEST/ALICE1TEST
Ionizing Particle Irradiation in NA50
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Severe degradation
only after 1.7 Mrad in
two days
After 42 hours beam
was off for a couple of
hours, some recovery
visible
Drop in lower plot
below 130 before 50
hours is artifact, all
pixels responded
Irradation continued
to about 3 Mrad after
none of the pixels
responded any more
Walter SNOEYS - CERN - EP - MIC
Ionizing Particle Irradiation in
NA50 : anneal
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Some pixels start to
respond after 1 week
of annealing at room
temperature
The last week of
anneal was carried out
at 100 C => slope
change
Walter SNOEYS - CERN - EP - MIC
Irradiation Degradation Mechanism
Measured NMOS transistor VT shift
D Vth [V]
MIETEC N-ch Enclosed
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
N8_0.5C
N8.5_0.7CL
N10.2_1.5C
N17.5_5CL
0
500 1000 1500 2000
Total Dose [krad(SiO2)]
Walter SNOEYS - CERN - EP - MIC
Irradiation Degradation Mechanism
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Introduced measured
Vt - shift data to
simulate degradation
Vt - shift causes
preamplifier feedback
to push shaper input
transistor out of
saturation
Confirmed by
correlation of
operating margin and
irradiation dose
Walter SNOEYS - CERN - EP - MIC
LHC2TEST/ALICE1TEST
Radiation Tolerance :
Summary
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Irradiation tests done with 10 keV X-rays,
Gamma 60Co, 6.5 MeV protons, and
electrons in NA50
No large increase in supply currents with
dose => rad tolerant layout techniques
prevent leakage
Serious degradation (= severe pixel
threshold increase) sets in only after ~600
krads with Xrays and ~1 Mrad or higher for
the other sources (e.g. 1.7 Mrad for NA 50
beam)
Walter SNOEYS - CERN - EP - MIC
LHC2TEST/ALICE1TEST
Radiation Tolerance :
Summary
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Degradation mechanism explained through
Vt shift
Significant recovery (annealing) after a
relatively short time
Walter SNOEYS - CERN - EP - MIC
8
8
6
6
mA
mA
ALICE2TEST Chip
Evolution of power supply currents
with X-ray dose
(10 keV X-rays at 4 krad/min)
4
4
2
2
0
0
0.01
0
5
10
15
20
25
30
dose (Mrad)
digital
digital during readout
analog
0.1
1
10
100
dose (Mrad)
digital
digital during readout
analog
Walter SNOEYS - CERN - EP - MIC
ALICE2TEST Chip
Evolution of average threshold,
threshold dispersion and noise
with X-ray dose
3400
electrons
electrons
3500
3300
3200
3100
0.01
0.1
1
10
100
350
300
250
200
150
100
50
0
0.01
dose (Mrad)
average pixel threshold
Walter SNOEYS - CERN - EP - MIC
0.1
1
10
100
dose (Mrad)
threshold dispersion (rms)
noise (rms)
ALICE2TEST
Radiation Tolerance :
Summary
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Irradiation tests done with 10 keV X-rays @
4 krad/min
No large increase in supply currents with
dose => rad tolerant layout techniques
prevent leakage
Functionality preserved up to 30 Mrad,
parametric degradation (noise and
threshold dispersion increase) acceptable,
also after anneal
Also confirmed in proton beam up to 1.5e15
protons/cm2
Walter SNOEYS - CERN - EP - MIC
Layout for Radiation Tolerance :
Design Implications
Modeling of Transistors in Enclosed Geometry
dV(x)
I  8xmCox(Vg V (x) VT )
dx
W2 / 2
Vd
dx
I   8 mCox  (Vg  V ( x )  VT ) dV ( x )
x
W1 / 2
Vs
8
W



W 2 
 L eff
ln 

 W1 
Walter SNOEYS - CERN - EP - MIC
Layout for Radiation Tolerance :
Design Implications
Modeling of Transistors in Enclosed Geometry
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I - V characteristics (SPICE models)
8
W

 
 L eff ln  W 2 


 W1 
Note : to obtain W/Leff = .1 …. IMPOSSIBLE !
=> accurate NMOS current mirrors difficult
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Matching : non-uniform current flow !
Noise
Before and after irradiation !
Walter SNOEYS - CERN - EP - MIC
Layout for Radiation Tolerance :
Design Implications
Circuit Density :
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Digital : there clearly is a penalty for the
same technology. However, one should
compare not to the same technology but to
a radiation hard/tolerant alternative.
Analog : example showed certain circuit
topologies (making use of accurate NMOS
mirrors for instance…) should be avoided.
In that case small penalty even for same
technology.
Number of metal layers plays a big role
Walter SNOEYS - CERN - EP - MIC
Layout for Radiation Tolerance :
Design Implications
CAD Environment (!!!)
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Digital library = full custom
Verification routines : DRC, extraction, LVS
ALL require some modification
Walter SNOEYS - CERN - EP - MIC
CONCLUSIONS AND
PERSPECTIVES
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Special layout + thin gate oxide = radiation tolerance
Special layout techniques have made a pixel readout
prototype implemented in a
- commercial 0.5 mm CMOS technology
radiation tolerant up to ~ 1 Mrad.
- commercial 0.25 mm CMOS technology
radiation tolerant up to 30 Mrad.
Density, power-speed performance, and radiation
tolerance
=> deeper submicron
Design implications
Note : Single event effects
Walter SNOEYS - CERN - EP - MIC
CONCLUSIONS AND PERSPECTIVES
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Thinner gate oxide helps to reduce
radiation induced transistor parameter
shifts and therefore significantly increases
radiation tolerance
Density, power-speed performance, and
radiation tolerance
=> deeper

submicron
Some issues not discussed : Single Event
Upset : will be very important in some of the
future LHC experiments and Single Event
Latchup
Walter SNOEYS - CERN - EP - MIC
ALICE2TEST
Radiation Tolerance :
Summary

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Irradiation tests done with 10 keV X-rays @
4 krad/min
No large increase in supply currents with
dose => rad tolerant layout techniques
prevent leakage
Functionality preserved up to 30 Mrad,
parametric degradation (noise and
threshold dispersion increase) acceptable,
also after anneal
Special layout techniques have made a
pixel readout prototype implemented in a
commercial 0.25 mm CMOS technology
radiation tolerant up to 30 Mrad.
Walter SNOEYS - CERN - EP - MIC