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TRAPPISTE Tracking Particles for Physics Instrumentation in SOI Technology Institut de recherche en mathématique et physique Center for Cosmology, Particle Physics and Phenomenology Prof. Eduardo Cortina, Lawrence Soung Yee 10 November, 2011 SCK-CEN Meeting 1 Hybrid vs. Monolithic Detectors - Integration problems - Production yield - Fragility 10 November, 2011 - Sensor and electronics isolation - “Non standard” process SCK-CEN Meeting 2 Monolithic Detector in SOI Technology Active layer: ~50nm Contains readout electronics n+ Buried Oxide (BOX): ~200nm Insulates circuit from detector p+ + + 10 November, 2011 + -- - Handle wafer: ~300µm Contains the detector. The backside metal is biased to deplete the detector. SCK-CEN Meeting 3 TRAPPISTE-1 2μm Fully Depleted SOI CMOS at WINFAB at UCL Shift register to control readout column by column. 3cm 8x8 matrix of 300μmx300μm pixel cells with 3 transistor readout. 10 November, 2011 3cm SCK-CEN Meeting 4 TRAPPISTE-2 0.2µm fully depleted (FD-SOI) CMOS by OKI Semiconductor, Japan 3T Matrix Standard 3-transistor readout chain 2.5mm Each pixel 150µm x 150µm CSA Matrix Charge sensitive readout chain amplifier Each pixel 150µm x 150µm CSA test area Amplifiers chain with standard and low voltage threshold transistor. Transistor test area 7 column source tied transistors. 10 November, 2011 2.5mm SCK-CEN Meeting 5 Pixel Matrix A matrix of pixels with three transistor readout. - Readout controlled by a shift register to activate on column at a time - Different shaped implants to improve breakdown voltage 10 November, 2011 SCK-CEN Meeting 6 Readout Chain Detector Charge Sensitive Amplifier Shaping Amplifier Cdif Cf Rdif Digitizer Vth Rint Cint Rf 10 November, 2011 SCK-CEN Meeting 7 Amplifier Measurements TRAPPISTE-2 Data Parameters Power supply VDD Detector Capacitance Cd Detector Signal Feedback resistance RF Feedback capacitance CF Specification +1.8 0.25pF 1 MIP ( 23.000e-) >100MΩ 37.57fF Injected charge (1MIP) Output of shaper Output of CSA 10 November, 2011 SCK-CEN Meeting 8 CSA DC Sweep DC Sweep Characterizations - Simulations match measurements - Shift of transfer curve with bias ring voltage 10 November, 2011 SCK-CEN Meeting 9 Test System FPGA board to program test routines. Main board: - Voltage and current sources - DACs to set appropriate biases - ADC to read output voltages Daughter board to accommodate test devices and package types. 10 November, 2011 SCK-CEN Meeting 10 Schedule Start of TRAPPISTE project 2008 TRAPPISTE-1 2009 TRAPPISTE-2 2011 TRAPPISTE-3 Laser and beam tests L. Soung Yee PhD 2012 TRAPPISTE-4 P. Alvarez PhD (UAB) 2013 TRAPPISTE-5 (engineering model) 2015 Manpower required: 1 Post-doc + 1 PhD 10 November, 2011 SCK-CEN Meeting 11 Backup Slides 10 November, 2011 SCK-CEN Meeting 12 Measurement of Transistor Characteristics Influence of back bias on transfer curves and transistor parameters. 10 November, 2011 SCK-CEN Meeting 13 Discriminator Measurements Discriminator measurements - Output for various threshold voltages - Influence of bias on detector ring 10 November, 2011 SCK-CEN Meeting 14