Transcript Fast clear

DEPFET-Technology and Design
- Special requirements for DEPFETs within SuperBelle
- Technology and schedule
- Pixel designs for SuperBelle
- Radiation hardness
- Yield problems
Karlsruhe, 2.12.08
Rainer Richter HLL
DEPFET specific requirements
Thinned substrate:
to reduce multiple scattering
total signal charge @50µm: 4000e-
Noise:
total enc
: 100eread out electronics
: DCD-chip: noise ca. 35nA -> 75e- @ gq=400pA/eDEPFET noise
: < 50eshot noise (30e-) -> max. leakage 200nA/cm-2 @RT, 10µs frame time
(pixel size (50x100µm²)
Speed:
10µs/frame (half module)
-> 80ns readout cycle time
@80µm row pitch and 4fold read out
Z=0
Radiation damage:
ILC: 200krad (5 years) -> Investigation up to 1Mrad
SuperBelle: 10Mrad (?) - mostly ionizing radiation
hadronic damage is negligible
Karlsruhe, 2.12.08
Rainer Richter HLL
DEPFET productions for SuperBelle
First run (in 2009)
- backside pre processing: driven by SOI requirements - Clean room
-- wafer bonding and frontside thinning at Tracit
- frontside technology will be a copy of PXD5 technology – Clean room
- backside thinning and contacting – Application Lab.
Aim: test run
small prototypes and large demonstrators
- find the optimal design
- demonstrate feasibility in terms of yield and speed
- provide samples for the ‘full silicon module‘ construction tests
-
- First DEPFET run on thinned material
16 lithographic mask steps and 9 implantations
8 wafers
6 SOI wafer
2 reference wafer on standard bulk
-
Start: Beginning 2009
-
End: June 2010
Karlsruhe, 2.12.08
Rainer Richter HLL
SuperBelle Production run
Improved technology
12 large modules – outer layer (1 or 2 per wafer)
12 small modules – inner layer (2 per wafer in addition to the large ones)
20 wafers?
(yield estimate from big demonstrator chips on the previous run, final
module size)
Begin: 2011
End: Spring 2012
Karlsruhe, 2.12.08
Rainer Richter HLL
SuperBelle pixel design considerations
Speed requirements as tough as in ILC: frame readout time ≤ 10µs
Pixel size significantly larger than in ILC (24x24µm²) : 50x75µm²(typical, and
larger in z ….)
ILC:
address 2 rows in parallel -> doubles the speed and the number of
readout channels
Larger x-pitch allows further parallelisation
SuperBelle: 4 row address lines (gate and clear) are connected together
-> keep the ‘ILC pitch‘ for readout lines and DCD channels
Assuming a 75µm y-pitch a 300µm ‘detector strip‘ is read out at once
-> row processing time (read-clear-read) ≈ 80ns
Karlsruhe, 2.12.08
Rainer Richter HLL
Why not just expanding an ILC Standard Design?
example: common clear gate cell 50x75µm²
Irreducible cell concept
(sharing of Clear, Source
and Drain by neighboring
cells)
-> double (row) cell
4 row control possible
in interleaved mode
Most important layers:
p+ implants (source, drain)
n+ implants (clear)
Poly1 (clear gates)
Poly2 (Depfet gates)
Metal 1 (horizontal address lines)
Metal2 (vertical read out lines)
Karlsruhe, 2.12.08
Rainer Richter HLL
Larger pixel in y-direction !
Charge collection times short enough ?
DEPFET charge drift/diffusion times has to be compared to frame
readout time (10µs) in superBelle?
2D Simulations
Along y-axis (section through source-channel-drain)
75µm pixel size
50µm thick detector
Vs = 0V, Vd = -5V , Vg = 5V (collection state)
Karlsruhe, 2.12.08
Rainer Richter HLL
shifted DEPFET gate (y=27.5µm)
5000e/h generated at y=0 (source side)
ca. 300ns
collection time
(improvement
by a factor of
3)
Internal gate charge
Karlsruhe, 2.12.08
Rainer Richter HLL
shifted DEPFET gate (y=27.5µm)
5000e/h generated at y=75µm (drain side)
ca. 250ns collection
time (worse by
150ns)
Asymmetric
arrangement of
the gate
Internal gate charge
2/3 drain and 1/3
source
seems to be the
optimum
Karlsruhe, 2.12.08
Rainer Richter HLL
Potential during Clear I
cross section perpendicular to the channel
pixel width = 50µm
Required clear time ~20ns
Clear
Karlsruhe, 2.12.08
Clear
Gate
Internal
Gate
Rainer Richter HLL
Potential along the Channel during Clear I
in potential minimum of internal gate (0.6µm)
Potential gradient
of a few mV
-> drift time about
100ns
Sensitive to channel
length fluctuations due
to imperfect etching
Clearing in the given
time impossible!
Karlsruhe, 2.12.08
Rainer Richter HLL
‘Small width‘ design (as for ILC)
W = 10µm
Larger gaps to be filled
with n+ -Clear and floating
deep p
Most important layers:
p+ implants (source, drain)
n+ implants (clear)
Poly1 (clear gates)
Poly2 (Depfet gates)
Metal 1 (horizontal address lines)
Metal2 (vertical read out lines)
Karlsruhe, 2.12.08
Rainer Richter HLL
Space for 4 drain readout lines
Most important layers:
p+ implants (source, drain)
n+ implants (clear)
Poly1 (clear gates)
Poly2 (Depfet gates)
Metal 1 (horizontal address lines)
Metal2 (vertical read out lines)
Karlsruhe, 2.12.08
Rainer Richter HLL
High speed performance
High speed readout
=> high bandwidth
=> short shaping times
Thermal noise ~ 1/SQRT(t)
Measurements of a single pixel with an external high bandwidth amplifier.
Intrinsic DEPFET noise sufficiently low for high speed operation
ENC
Signal (50 mm):
~ 40 e- @ t=20ns (50MHz)
4000 e-
Fast clear:
-> necessary for high speed operation
Complete clear achievable in < 10 ns
Noise due to residual charge
However:
Present clear voltages rather high (>10V)
Design goal: lower clear voltages
(U > 10V not compatible with rad. hard
CMOS)
Karlsruhe, 2.12.08
Complete clear within 10ns
Rainer Richter HLL
Design with individual source and drain regions
giving up the shared source and drain concept
Separation of
source and drain in
different rows
-> shorter charge
collection times
A bit maller readout
capacitances
Most important layers:
p+ implants (source, drain)
n+ implants (clear)
Poly1 (clear gates)
Poly2 (Depfet gates)
Metal 1 (horizontal address lines)
Metal2 (vertical read out lines)
Karlsruhe, 2.12.08
Rainer Richter HLL
Drift in the deep p region in neighborhood of Drain (I)
Vback = -30V
Typical drift behavior
1.) vertical 2.) lateral
tdrift < 10ns
Source
Karlsruhe, 2.12.08
Clear
Gate
deep p
Rainer Richter HLL
Bricked designs possible
6% longer readout lines
Most important layers:
p+ implants (source, drain)
n+ implants (clear)
Poly1 (clear gates)
Poly2 (Depfet gates)
Metal 1 (horizontal address lines)
Metal2 (vertical read out lines)
Karlsruhe, 2.12.08
Rainer Richter HLL
Charge collection with big clear contacts
depth
drift chamber like potential distribution
Internal
Gate
Clear
Source
Gate
Clear
deep p
drift times in nanosecond range
Karlsruhe, 2.12.08
Rainer Richter HLL
Capacitive Coupling between Clear and Cleargate (i)
Clear n+ implant (green)
Poly 2 (yellow)
Experiences from clocked
cleargate matrices (XEUS and ILC)
Few volts cleargate clocks are sufficient
to facilitate the clear process significantly.
DVCLG = VCL * CCL-CLG/CCLGtot
Rough estimate: 30%
2D-clear-simulations: ok
Karlsruhe, 2.12.08
Rainer Richter HLL
Capacitive Coupling between Clear and Cleargate (ii)
You should see here
Meander resistors (500kOhm)
connected to the Cleargate
t >> tClear
Common VRes defines VCGoff and
can be used to adjust for irradiation
induced threshold shifts
C3G cells on one of the
big 21x20mm² chips
But: wider cell variant
32x24µm²
Karlsruhe, 2.12.08
Rainer Richter HLL
Stefan Rummel: Cd Spectrum
two regions in one 64x128 matrix
Standard clocked Clear gate
gq =300pA/e-
Karlsruhe, 2.12.08
Capacitive coupled Clear gate
gq =450pA/e-
Rainer Richter HLL
Noise and pedestal distributions
Karlsruhe, 2.12.08
Rainer Richter HLL
Capacitive coupled clear - SuperBelle matrix
Karlsruhe, 2.12.08
Rainer Richter HLL
Karlsruhe, 2.12.08
Rainer Richter HLL
Pixel Design Classification
1) Stretched ILC design
Advantage: small changes compared to ILC
Drawbacks: larger collection times, not suitable for long pixels, no brickking
higher drain capacitances
2) Individuell DEPFET design
Source/Drain of neigboring pixels separated, Clears shared
A) Common Cleargate
B) Capacitive couples Cleargate
Z-length variations (50µm, 100µm, 150µm)
Mixed sizes within one matrice (50µm and 150µm)
Bricked designs
low drain cap – floating regions with deep p implantations only
larger drain cap - floating regions with deep p and shallow p implantation
(more rad hard)
About 60 test chips available, degree of permutations not yet fixed
Karlsruhe, 2.12.08
Rainer Richter HLL
Radiation issues
Bias applied
Annealing @RT ~9V
Thresholddispersion is significantly reduced!
Karlsruhe,
SBELLE
Meeting,2.12.08
Karlsruhe
Rainer Richter HLL
Stefan Rummel; MPI for Physics
26
What can we do?
1) Compensation of the threshold voltage shift by appropriate gate voltage and clear gate
voltage shifts
to cope inhomogeneous radiation: different compensation voltages for differently
irradiated regions
rather inconvenient, not suitable for dispersion along gate lines and for intrinsic
dispersions of the DEPFETs
2) Take and digitaly store (in certain time intervalls) pedestal currents on the read out chip
convert them back by a DAC and subtract them at the input
It‘s additional efford but according to Ivan Peric doable
Advantage: technology inherent dispersions can be compensated too
But: no solution against threshold voltage dispersions of the Clear gates, adjustment is crucial
3) Improve the intrinsic radiation tolerance of the DEPFET
Karlsruhe, 2.12.08
Rainer Richter HLL
Irradiation of thinned oxides
MOS-C
Bias effect @1Mrad
25
6.00E+012
flat band voltage
positive oxide charge
20
5.00E+012
Dose=1 Mrad
dox=86nm
gate
4.00E+012
-VFB (V)
Only oxide: 86nm
3.00E+012
DEPFET- matrix
reset
off
off
on
reset
off
off
-2
Nox (cm )
15
(Q. Wei)
nxm
pixel
10
off
off
2.00E+012
VGATE, ON
VGATE, OFF
5
1.00E+012
-10
-5
0
5
10
15
IDRAIN
drain
VCLEAR, ON
VCLEAR, OFF
VCLEAR-Control
0 suppression
output
Vg (V)
on mode
(readout)
off mode
(collection
1/nrow * t
(nrow-1)/nrow * t
Karlsruhe, 2.12.08
Rainer Richter HLL
Irradiation of thinner dielectrica (Q. Wei)
1 Mrad 20keV X-rays
Flat Band Voltage Shift
35
MOS - 86nm Oxi
?
MOS - 100nm Oxi
Vgate=0V
MNOS - 86nm Oxi & 10nm Nitride
30
MNOS - 100nm Oxi & 10nm Nitride
10 Mrad
25
Flat band voltage shift vs. radiation dose
M N O S - 86nm O xi& 10nm N itride
20
15
0,75
10
V fb (V )
Vfb (V)
1
5
0
-10
-5
0
5
10
15
0,5
0,25
Vg (V)
tox=86nm, tni=10nm
0
0
250
500
750
1000
Radiation dose (krad)
Further radiation test up to 10Mrad by Q. Wei still this year
But: gq ~ sqrt(tox) , can be compensated with higher currents
and/or shorter gate length
Karlsruhe, 2.12.08
Rainer Richter HLL
Test project – thin dielectrica
Aim: find the best oxide/nitride composition for the SB productión run
- radiation of MOS transistors and Capacitors
- study of IV curves (early breakdowns) before and after irradiation
Start values: 86nm/10nm (Wei‘s investigations)
Oxidation
Deepn Implant (‘internal gate‘) unmasked
Nitride deposition
LTO deposition
- graded thinning of LTO below the thickness needed to mask nitride etching
slowly pulling the wafers out of the etchant (neue Naßbank)
-> gradient of the nitride thickness over the wafer after nitride etch
Polysilicon deposition, etching, oxidation
Shallow p Implantation – threshold adjustment (masked)
P+ implantation for S/D regions (masked)
contact openings
metallization
5 masks, 4 implantations
Karlsruhe, 2.12.08
Rainer Richter HLL
Yield problem I - Polysilicon roughness
Poly I + II edges and surfaces
Karlsruhe, 2.12.08
Rainer Richter HLL
wet etch vs plasma etch
Etching after recristallization necessary
Grit removal (deFreckel etch) necessary
Etching before recristallization possible
no remaining grit
We expect: better homogeneity of pedestal currents and clear behavior
2 SOI wafers of 6 should get plasma etched poly
Karlsruhe, 2.12.08
Rainer Richter HLL
Yield problem II – metal 1 / metal 2 shorts
W91 D11 512x512 (wide format)
Vclear=15V 20x
Vclear=10V 5x
Always triplets!
above and beneath
2 rows apart
(2 drain lines per columns
every second row
connected to one drain line
Karlsruhe, 2.12.08
Rainer Richter HLL
PXD5 – II
finished
Shorts on big 256k matrices between:
metal1 and metal2
poly1 (Clear Gate) and poly2 (Gate)
diodes - Source/Drain vs Clear
Yield:
9(15)
bigger cell sizes (32x24µm²): 7(9)
PXD5-I; 1 (15)
Reasons for improvement not clear !
Karlsruhe, 2.12.08
Rainer Richter HLL
Summary
SuperBelle is an interesting and challenging project
- rad hard gate insulator development
Technology driver for DEPFET
Karlsruhe, 2.12.08
Rainer Richter HLL
Internal amplification - Gq
Good agreement between measurement and simulation
1nA/e- is within reach
Karlsruhe,
2.12.08
Pixel 09
, September
22-26, 2008 - FNAL
Stefan Rummel; MPI for PhysicsRainer Richter HLL36
Capacitive Coupling between Clear and Cleargate (iii)
Test chip: pMOS – Sourcefollower test structure connected directly to CLG
Karlsruhe, 2.12.08
Rainer Richter HLL
Karlsruhe, 2.12.08
Rainer Richter HLL
PXD6 structures
-
(Small) selection of ILC matrices to of devices on thinned substrates
128x128 matrices (7x10mm²)
Common clear gate matrices
Capacitively coupled matrices
SuperBelle matrices
test arrays: 128x128
varying pixel gemetries
testing bricked pixels
evaluating different designs (individual S/D, shared S/D, C3 pixels …)
large arrays – half of a full size module (12x35mm²) :
for yield estimations and speed evaluations
Karlsruhe, 2.12.08
at least 2
Rainer Richter HLL
Comparison: COCG vs C3G
SNR vs VG
(Cd Source)
Vsource = 7V
Karlsruhe, 2.12.08
Rainer Richter HLL
Irradiations for ILC: Electrical characteristics
Pixel 09
, September
22-26, 2008 - FNAL
Karlsruhe,
2.12.08
Stefan Rummel; MPI for PhysicsRainer Richter HLL41
Switcher III and DCD2
Switcher III (Heidelberg):
-Radiation hard (AMS 0.35 mm, rad hard layout)
-10V swing (-> stacked transistors)
-Low power (“0” standby current)
-Fast settling (<4ns at 10 pF)
-128 channels, compact layout (1.24 x 5.8 mm2)
-Full chip produced and tested
rad hardness tested > 600kRad!
Current Readout Chip, DCD2 (Heidelberg):
-Improved noise performance of regulated cascode
especially at large load capacitances
expect 40-50 pF for 5cm long matrices
simulation: 34 nA @ 40 pF
-Fully differential analog processing
-Fast 8 bit ADC (12.5MHz) for each channel
-144 channels, 5mW per channel
-No hit processing (done in a FPGA)
-Rad hard layout (analogue part), UMC018 process
-Test chip produced (72 ch), under test
Karlsruhe, 2.12.08
Rainer Richter HLL
DNMOS (annular)
G
D
S
S
B
n+ p+
pG
nD
p- sub
Karlsruhe, 2.12.08
Rainer Richter HLL
Sw4 measurements
switches between 0 and 15 V
Karlsruhe, 2.12.08
switches between 15 and 0 V
Rainer Richter HLL
DCD2 performance
ENC:
95 e- @ 44pF
80 e- @ 0pF
was ~ 250 e- for CURO (@ 0 pF)!
ILC: 1000 pixel & 5cm readout line:
sBelle: 120 pixel & 3.55 cm readout line:
Karlsruhe, 2.12.08
~ 44pF
< 44 pF
Rainer Richter HLL
ILC (1Mrad) -> SuperBelle (10Mrad)
4 neighboring DEPFET within a mini matrix (Stefan Rummel)
with almost realistic biassing
rather thick oxides:
usually leads to Vth > 20V@1Mrad
With DEPFET much better situation:
- very low electric fields, recombination of
generated electron/hole pairs in the oxide
- sandwich dielectricum SiO2/Si3N4
-> compensation of positive oxide charge by
electrons trapped in the nitride
Dispersion of 1V
(gm 30µS)
Repitition of the radiation test at even more
realistic biassing
more statistics !
Karlsruhe, 2.12.08
Rainer Richter HLL
Parasitic Capacitances
Example: Drain Capacitance y-pitch 75um, 512 rows
51pF
Karlsruhe, 2.12.08
Rainer Richter HLL
High speed performance
High speed readout
=> high bandwidth
=> short shaping times
Thermal noise ~ 1/SQRT(t)
Measurements of a single pixel with an external high bandwidth amplifier.
Intrinsic DEPFET noise sufficiently low for high speed operation
ENC
Signal (50 mm):
~ 40 e- @ t=20ns (50MHz)
4000 e-
Fast clear:
-> necessary for high speed operation
Complete clear achievable in < 10 ns
Noise due to residual charge
However:
Present clear voltages rather high (>10V)
Design goal: lower clear voltages
(U > 10V not compatible with rad. hard
CMOS)
Karlsruhe, 2.12.08
Complete clear within 10ns
Rainer Richter HLL
DEPFET intrinsic noise at high Bandwidth
ENC @ 50MHz <50eAssuming 50µm thick Silicon S/N > 80
Karlsruhe,
2.12.08
Pixel 09
, September
22-26, 2008 - FNAL
Stefan Rummel; MPI for PhysicsRainer Richter HLL49