Transcript Slides - Agenda INFN

Alessandra Lattuca
Università degli studi di Torino – INFN (To)
Tor Vergata - Rome, April 10, 2015
On behalf of the ALICE Collaboration
IMPIEGO DEI MAPS PER L’UPGRADE
DELL’ITS
1
OUTLINE




Background and Motivations for the ALICE ITS
UPGRADE
Overview of the Monolithic Active Pixel Sensor
(MAPS) technology
High Speed Data Transmission
Summary
2
ALICE DETECTOR
MAIN GOAL: DETAILED STUDY OF THE QUARK-GLUON
PLASMA (QGP) PRODUCED IN HEAVY ION
COLLISIONS
3
THE PRESENT INNER TRACKING SYSTEM
• Primary vertex
Localization
• Secondary vertex
reconstruction
• Particle Identification
Layer
Type
r (cm)
±z (cm)
1
Hybrid pixel
3.9
14.1
2
Hybrid pixel
7.6
14.1
3
Drift
15.0
22.2
4
Drift
23.9
29.7
5
Strip
38.0
43.1
6
Strip
43.0
48.9
Limitations:
Read-out rate
Capability is 1
kHz;
Material Budget
per layer: 1.14%X0
4
THE NEW ITS
INNER BARREL
OUTER BARREL
Layer
Type
r (cm)
z (cm)
0
MAPS
2.24 – 2.67
27.1
1
MAPS
3.01 – 3.46
27.1
2
MAPS
3.78 – 4.21
27.1
INNER
BAR
REL
Inner
Layers
OUTER
BAR
REL
Middle
Layer
3
MAPS
19.44 – 19.77
84.3
4
MAPS
24.39 – 24.70
84.3
Outer
Layer
5
MAPS
34.23 – 34.54
147.5
6
MAPS
39.18 – 39.49
147.5
 Material
Budget per
layer
0.3%X0
(Inner
Barrel)
 Read out
rate: 50kHz5
STANDARD MAPS
Thin Sensor 
Thermal diffusion
N-well collection diode 
NO P-Mos transistors allowed 
6
QUADRUPLE WELL MAPS
TowerJazz 0.18 µm CMOS technology
 Improved TID due to the smaller
technology node (Gate oxide < 4 nm)
High resistivity epitaxial layer. The
resistivity ranges between 1 kΩ ∙cm and
6 kΩ ∙cm so that a sizeble part of the
sensor volume can be depleted
Thermal diffusion + Reverse Bias application to speed up the collection time
N-well collection diode
 6 metal layers option in order to have high density and low power digital circuits
DEEP PWELL for P-Mos implementation 
7
ALPIDE CHIP
• Matrix of 512 rows x 1024 columns
• Until now, 2 prototypes of ALPIDE were fabricated and a third version is under
development
• Pixel dimension (pAlpide1 e pAlpide2): 28 x 28 µm2
• 4 different pixel flavours
• New Low Power Priority Encoder read-out architecture
8
LAST PROTOTYPE OF ALPIDE
SLOW CONTROL &
CLK DISTRIBUTION
DTU
9
HIGH SPEED DATA TRANSMISSION

Phase Locked Loop (PLL) + Serializer + Low Voltage Differential
Signaling (LVDS) Driver

The DTU will be implemented for both ITS chip design options,
ALPIDE and MISTRAL –O

Send data from the chip periphery to the patch panel

Need to drive data at :
• the targeting speed of 1.2 Gbps along a 0.3 m Al Flex Printed
Citcuit + 5m Cu twinax cable (Inner Barrel);
• the targeting speed of 400 Mbps along a 1.5 m Cu Flex Printed
Circuit + 5m Cu twinax cable (Outer Barrel)
10
DATA TRANSMISSION UNIT (DTU) BLOCK DIAGRAM
11
LVDS : PRINCIPLE OF OPERATION
 LVDS : Low Voltage Differential Signaling (TIA/EIA-644)
Current steering
Principle
 Less sensibility to the
common mode noise
 Less EMI
12
ANALYZING THE TRANSMISSION: EYE DIAGRAM
13
FIRST VERSION – SUBMITTED IN MARCH2013 WITH AN
ENGEENERING RUN TO WHICH CERN CONTRIBUTED
DRIVER
Additional
switches for the
Slew rate Control
14
2 LVDS DRIVER VARIANTS SUBMITTED IN
MARCH 2013 & TESTED IN SEPTEMBER 2013
LVDS CHIP 1
LVDS CHIP 2
The difference between the two chips is in the receiver part. For the LVDS chip
1 the current which flows in the receiver has a fixed value of 1mA . In contrast,
for LVDS chip 2 it possible to select the current which flows in the circuit.
15
Bit rate (Mbps)
400
Diff. Amplitude (mV)
494
Unit Interval (ns)
2.5
Eye Width (UI)
0.99
Eye Height (mV)
457
Rise time (ps)
198
Fall time (ps)
183
Jitter (ps)
Current (mA)
0.014
4
Bit rate (Mbps)
1000
Diff. Amplitude (mV)
450
Unit Interval (ns)
1
Eye Width (UI)
0.93
Eye Height (mV)
400
Rise time (ps)
151
Fall time (ps)
144
Jitter (ps)
0.11 16
Transmission quality degrades by increasing the
transmission speed and reducing currents
17
LVDS-BLOCK DIAGRAM – ENGEENERING RUN NOVEMBER 2014
S
E
R
I
A
L
I
Z
E
R
18
PRE- EMPHASIS
A
A_D
A
A_D
I_Out
0
0
-IMD
0
1
-IMD-IPE
1
0
IMD+IPE
1
1
IMD
Pre-emphasis is needed to overcome RC
limitations of the long transmission lines.
We will add/subtract a small amount of
current ONLY if two subsequent bits are
different. For this reason we need to know
the bit stream A and its delayed copy A_D
19
POST Twinax
Simulation Conditions:
•Calibre view
•Nominal Corners
•Driver Code: 9 (4 mA)
•Pre-Emphasis Code: 4 (2mA)
•30 cm Al FPC + 5m Coax Cab.
•Bit rate: 1.2 Gbps
Parameter
Value
Hor. Aperture (ps)
746.6
Vertical Aperture (mV)
564.6
tr (ps)
516
tf (ps)
535
bit period
827.3
jitter
67.2
20
LVDS TEST CHIP SUBMITTED IN NOVEMBER 2014
LVDS driver test chip
submitted in November
The driver will be tested by
using:
 A clock from the PLL
 An external PRBS and the
same signal delayed
FUTURE PLAN:
SUBMISSION in APRIL 2015
On the next prototype we will
include the driver without SR
control in the full DTU chain
(PLL + HS Serializer + Driver)
21
SUMMARY AND CONCLUSION
ITS Upgrade;
 MAPS technology;
 High Speed Data Transmission: so far two LVDS
driver standalone were submitted. At the end of
April 2015 the entire DTU will be integrated on the
third version of ALPIDE;
 The first LVDS driver prototype were tested where
the second prototype submitted in November
2014 will be tested in few weeks from now.
 The R&D program for the ITS Upgrade will end in
2015 in order to be ready for the chips
installation after the Long Shutdown 2, in 2018.

22
THANKS!
23
BIBLIOGRAPHY
[1] The ALICE experiment at CERN LHC - 2008 JINST 3 S08002
[2] Technical Design Report for the Upgrade of the ALICE Inner Tracking System
(CERN-LHCC-2013-024, 29 November 2013 )
[3] A. Tajalli, Y Leblebici, A slew controlled LVDS output driver circuit in 0.18 m
CMOS technology, Solid-State Circuits, IEEE Journal of 44 (2), 538-548
24
BACKUP SLIDES
25
PRESENT ITS LIMITATION
1. Limited read-out capabilities : 1kHz with 100% dead time
2. Poor resolution on the distance of closest approach.
26
HIT DENSITIES
27
LIMITATIONS OF THE PRESENT ITS

First layer radius : 3.9 cm

Read out rate: 1kHz

Pixel Size: 50 x 425 µm2

Material Budget per layer: 1.14%X0

Power Consumption: 500 mW/cm2
28
HI-LHC: HIGH LUMINOSITY LHC PROJECTS
L = 2-3 x 1034 cm-2 s-1
Interaction rate = 50 KHz
29
TOWARDS THE NEW ITS

First layer radius : 2.2 cm

Pixel Size: 28 x 28 µm2

Material Budget per layer: 0.3%X0

Power Consumption: < 300 mW/cm2

Read out rate: 50kHz
30
SPECIFICATIONS OF THE ITS
Parameter
Spec.
Unit
Line rate Inner Barrel
1.2
Gbps
Line rate Outer Barrel
400
Mbps
Load Termination
100 ± 10%
Ohm
T. Line
Lenght
(mm)
Material
Model
FPC
300
Aluminium
MTline
Twinax
5000
Copper
Nport – S
parameters
FPC
1500
Copper
MTline
Twinax
5000
Copper
Nport – S
parameters
Inner Barrel
Outer
Barrel
31
CHARACTERISTICS LVDS
DRIVER
PRE-EMPHASIS
Param.
Min
Max
Param.
Min
Max
VIS
0V
1.8 V
VIS
0
1.8
IOUT
2 mA
5 mA
IOUT
1 mA
2.5 mA
VOS (SS)
1V
1.2 V
Bit Rate
400 Mbps
1200 Mbps
∆VOS (SS)
-50 mV
+ 50 mV
Bit Rate
400 Mbps
1200 Mbps
32
CHARACTERISTICS
DRIVER
Param.
Min
Max
VIS
0V
1.8 V
IOUT
2 mA
8 mA
VOS (SS)
980 mV
1209 mV
∆VOS (SS)
-20 mV
+ 20 mV
VOS (PP)
150 mV
tpZH
0.35 ns
8.4 ns
tpZL
0.25 ns
0.7 ns
tpHZ
0.85 ns
1.3 ns
tpLZ
0.85 ns
1.35 ns
RECEIVER
Param.
Min
Max
VICM
0V
1.8 V
VIT+
50 mV
VIT-
-50 mV
VIS
LVDS
LVDS
VOUT
0 V (L)
1.8 V (H)
tpEH
0.25 ns
0.55 ns
tpHD
0.7 ns
2.6 ns
Duty Cycle 46%
51%
33
Definition
VIS
Input Voltage Swing
VICM
Input Common Mode
VOS
Steady-state CM output voltage
∆VOS(SS)
Variation on the steady-state CM output voltage between logic
states
VOS(PP)
Peak-to-peak common mode output voltage
VIT+, VIT-
Input voltage threshold
VOUT
Voltage at the receiver output
IOUT
Current driver by one driver
tPZH
Enable time, High impedence to high level output
tPZL
Enable time, High impedence to low level output
tPHZ
Disable time, High level to high impedence output
tPLZ
Disable time, Low level to high impedence output
tPEH
Enable time, Switch on to high level output
tPHD
Disable time, Switch off from the high level output
34
THE INNER TRACKING SYSTEM (ITS)
•Primary vertex
Localization
•Secondary vertex
reconstruction
•Particle Identification
35
TEST SETUP
•Agilent 81133A
3.35 GHz Pulse Pattern Generator
• Tektronix MSO/DPO70000 Digital &
Mixed Signal Oscilloscope
• two 50 cm Cu coaxial cable
36