Transcript Expo Poster - PowerPoint - Senior Design

Reconfigurable Computing for Space
Chris Canine, Cameron Dennis, Terseer Ityavyar
Sponsored by Dr. Greg Donohoe, NASA, University of Idaho CAMBR
Purpose
The Product
Goal:
Provide a proof of concept design and documentation that
highlight the benefits of using a low-voltage differential serial
communications scheme rather than standard single-ended
parallel interconnect.
Specifications:
•Transfer data at a speed of 800 Mbps from either of two
transmitting nodes to either of two receiving nodes
PCB Specifications
DC/DC Converters
Provide efficient, point of
use power conversion from
+12V to required voltage.
Includes enable and trim.
Size: 12” W x 10.5” H
Layers: Six w/ two planes
Smallest Trace: 7 microns
# of Components: 398
LVDS Crossbar
Retransmits incoming data
to receiving FPGAs. Can
act as splitter, repeater or
crossover as needed.
LCD Display Screen
Allows the board to display
the number of errors during
the Bit Error Rate Test, or
other information needed.
Serializer/Deserializer
Serializes 16-bit parallel
data and clock into a serial
stream at 1.25Gbps. Also
recovers data at receiver.
•Show the stability of the system with a Bit Error Rate Test
giving no errors in a 15 minute period.
•Deliver documentation comparing serial differential signaling
and parallel single-ended signaling on the basis of power
consumption and circuit board area.
Decoupling Capacitors
Spartan IIE FPGAs
Provide quick, temporary
energy during high power
demand. Reduces effects
of under-voltage situations.
Generate the semi-random
data used during the BERT
and control the sending and
receiving of data.
Solution
Main Components
Low Voltage Differential Signaling (LVDS)
Transmitting/Receiving Nodes:
A widely recognized standard which uses differential current direction to represent logic
Four Xilinx Spartan IIE FPGAs
levels. This allows very high speed serial data to be sent through two 100 ohm matched Serializer/Deserializers:
impedance traces, using approx. 8 times less space than parallel signaling.
Four National DS92LV16’s
Pros
Cons
•
350mV switching results in fewer power losses •
Matched impedance lines are more difficult to
•
Differential design creates little noise and rejects
lay out when creating PCB
outside interference
•
Requires that the components used support the
•
Uses only two lines, no matter what the data
standard and may require component changes
transfer rate is
3.5mA
Tx
+
350mV
3.5mA
-
Rx
LVDS Crossbar:
One National SCAN90CP02
Power Supply:
+12V Power Input
Twelve Datel LSN DC/DC Converters
Various Decoupling Capacitors
Basic LVDS communication
The team would like to thank the following
people for their contributions and help:
Dr. Joe Law, Dr. Herb Hess, Greg Klemesrud and John Geidl