Transcript Slide 1 - Indico

NxN pixel demonstrator
N
N
N
MUX
MUX
N
N
MUX
Addr.
Hit Reg1
serialize
Hit Reg2
Digital processing
MUX
Addr.
Hit Reg1
Hit Reg2
Addr.
Hit Reg1
Hit Reg2
DLL
Addr.
Hit Reg1
Ref CLK
78.125 MHz
Hit Reg2
128
N
LVDS
Time to Digital Converter (2)
• Tapped delay line
7
7-bit encoder
– 128 cells, 100ps
• Two hit registers
trigger
– One per both leading
and trailing edge
• 7 bit encoding
Hit Register 1
t0,t1,t3,…,tN-2,tN-1
Ref CLK
trigger
DLL
Hit Register 2
7
7-bit encoder
Delay Locked Loop - DLL
• Delay locked loop
– Voltage controllable
delay line (VCDL) of
128 delay cells
– Phase detector
– Charge pump
– Output buffers Ref CLK
t0
t1
tN-2
tN-1
VCDL
τ0
τ1
τN-2 τN-1
UP
PD
CP
DOWN
DLL CLK
VCTRL
Time to Digital Converter
• Christian’s TDC downscaled to 100ps
– Only delay cell and its bias circuit need to be redesigned
• Device sizes scaled down by factor of 10
– pmos loads 1.2 µm, nmos current source 1.2 µm, input pair
nmos 2 µm
• Ibias = 47 µA, Vsupply = 1.2 V
– 56 µW per delay cell
• 7.2 mW for 128 delay cells (corresponding to a 12.8 ns clock period
= 78.125MHz)
– Scaled down from 1.64 mA (2 mW)
• With slide difference in Current Density (times 4) due to the
impractical device dimensions
• Delay τD = 98 ps
– Easily adjusted to 100 ps with control voltage
Delay Cell Output
Delay Buffer Output – full cycle
Summary of Delay Cell
• Device sizes scaled down by factor of 10
– pmos loads 1.2 µm, nmos current source 1.2 µm, input pair nmos 2 µm
• Ibias = 47 µA, Vsupply = 1.2 V
– ~56 µW per delay cell
• 7.2 mW for 128 delay cells (corresponding to a 12.8 ns clock period =
78.125MHz)
– Scaled down from 1.64 mA (2 mW)
• With slide difference in Current Density (times 4) due to the impractical
device dimensions
• Delay τD = 98 ps
– Easily adjusted to 100 ps with control voltage
• Buffer
– 36.22 µA
– Appears to be enough to drive all the 90 hit registers (single-ended)
Hit Registers – Single-Ended
• Christian’s design made for 32 cells
– Each hit register consists of 32 DFFs
• 32 x 7 x 7 (µm)2 = 225 x 7 (µm)2
• In our design 2 x 45 Hit registers (each
128 DFFs) covering all 45 columns
– 128x7x7 (µm)2 = 900 x 7 (µm)2
– 90x900x7 (µm)2 = 900 x 630 (µm)2
• Total average power consumption for 90
single-ended hit registers = 67 mW
Hit Registers – Differential
• Differential hit register
– Two possible designs:
• Differential with CMOS logic output (full swing 0 – 1.2V)
• Differential with CML input and output (low voltage swing 0.8V –
1.2V)
– Total average power consumption of ~950 mW (increase by a
factor 14!)
– CML: Decreases the noise by a factor of 2/3 (2 peak noise, 3
rms noise)
– CMOS: Decreases the noise by factor 1.1/1.6
iN_peak (µA)
iN_rms (µA)
Pav (µW)
SE
33.684
3.355
5.84
DIFF
30.789
2.105
80.62
DIFF_CML
16.447
1.240
83.71
Differential or Single-ended?
•
•
•
Ground line noise through 1nH
inductance
Red: single-ended DFF
Orange: differential DFF w/ CMOS logic
output
–
•
Small signal levels only at input stage
Blue: differential DFF w/ CML output
–
Small signal levels at input and output
stages
Differential or Single-ended?
• Differential:
– Lower rms noise – high
power consumption
– Access to digital libraries
• Differential CML:
– Low peak and rms noise –
high power consumption
– No access to digital
libraries
• Every digital circuit needs
to be re-designed
differential
• Single-ended:
– Access to digital libraries
– Low power - high noise
BUT:
– All digital logic is out side
the pixels
• All pixels are purely
analog
– No analog circuits outside
the pixels
 Easy to isolate digital and
analog parts
- Separate power supply
and ground lines
- Guarding between pixel
array and periphery
Summary of TDC
• Differential Voltage Controllable Delay Line (VCDL)
– 128 differential delay cells
• Hit registers
– 2 regs per column (45 columns) => 90 Hit regs
– Average power consumption of 67 mW
• Simulated with each register changing its state once per clock cycle for ten
cycles
– Usually not all register change state and not all register banks are active every
clock cycle => average power consumption may be much less
• Total average power consumption
– 128 delay cells w/ buffers: 128 x 85 µA x 1.2 V = 13 mW
– 2 x 45 Hit register: 67 mW (differential: 964 mW)
– Total of ~80mW (differential: 977 mW)
The End
Differential or Single-ended?
• Genuinely differential means:
– Symmetric (exactly 180 degree phase difference)
signals biased with common current source
• Importance of mismatch
– Not complementary out-of-phase full-swing CMOS
signals
• Two benefits in CML signals
– Symmetric differential signals cancel the even order
components of noise and interference
– Current starving and small signal levels
• Decreasing the voltage swing, switching current and
therefore switching noise (PSRR)