Transcript EE208 Chapter 4 - Combinational Logic

1
EE 208 – Logic Design
Chapter 4
Combinational Logic
Sohaib Majzoub
What is a Combinational network?
X1
X2
Xm
Combinational
Network
Z1
Z2
Zm
Combinational Network: A stateless network (it does not
have a memory). The output is completely determined by the
values of the input.
• Output at time t depends only on input at time t
Sequential Network: The network stores an internal state.
The output is determined by the input, and by the internal
state. (it has a memory)
• Output at time t depends on input at time t and output at time t-1
2
3
Combinational Circuits Analysis and
Design
• Analysis
– Given a circuit, find out its function
– Function may be expressed as:
A
B
C
F1
A
B
C
A
B
A
C
F2
B
C
• Boolean function
• Truth table
• Design
– Given a desired function, determine its circuit
– Function may be expressed as:
• Boolean function
• Truth table
?
?
?
Analysis Procedure
4
• Boolean Expression Approach
A
B
C
A
B
C
A
B
F1
T2=ABC
T1=A+B+C
T3=AB'C'+A'BC'+A'B'C
F’2=(A’+B’)(A’+C’)(B’+C’)
A
C
B
C
F2
F2=AB+AC+BC
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
Analysis Procedure
• Truth Table Approach
A= 0
B= 0
C= 0
A= 0
B= 0
C= 0
0
A B C
0 0 0
0
0
F1
0
1
A= 0
B= 0
0
A= 0
C= 0
0
B= 0
C= 0
0
0
F2
5
F1
0
F2
0
Analysis Procedure
• Truth Table Approach
A= 0
B= 0
C= 1
A= 0
B= 0
C= 1
0
A= 0
B= 0
0
A= 0
C= 1
0
B= 0
C= 1
0
1
1
F1
1
1
0
F2
A B C
0 0 0
0 0 1
6
F1
0
1
F2
0
0
Analysis Procedure
• Truth Table Approach
A= 0
B= 1
C= 0
A= 0
B= 1
C= 0
0
A= 0
B= 1
0
A= 0
C= 0
0
B= 1
C= 0
0
1
1
F1
1
1
0
F2
A
0
0
0
7
B
0
0
1
C
0
1
0
F1
0
1
1
F2
0
0
0
Analysis Procedure
• Truth Table Approach
A=0
B=1
C=1
0
A=0
B=1
C=1
1
A=0
B=1
0
A=0
C=1
0
B=1
C=1
1
0
F1
0
0
1
F2
A
0
0
0
0
8
B
0
0
1
1
C
0
1
0
1
F1
0
1
1
0
F2
0
0
0
1
Analysis Procedure
• Truth Table Approach
A= 1
B= 0
C= 0
0
A= 1
B= 0
C= 0
1
A= 1
B= 0
0
A= 1
C= 0
0
B= 0
C= 0
0
1
F1
1
1
0
F2
A
0
0
0
0
1
9
B
0
0
1
1
0
C
0
1
0
1
0
F1
0
1
1
0
1
F2
0
0
0
1
0
Analysis Procedure
• Truth Table Approach
A= 1
B= 0
C= 1
A= 1
B= 0
C= 1
0
A= 1
B= 0
0
A= 1
C= 1
1
B= 0
C= 1
0
0
1
F1
0
0
1
F2
A
0
0
0
0
1
1
10
B
0
0
1
1
0
0
C
0
1
0
1
0
1
F1
0
1
1
0
1
0
F2
0
0
0
1
0
1
Analysis Procedure
• Truth Table Approach
A= 1
B= 1
C= 0
A= 1
B= 1
C= 0
0
A= 1
B= 1
1
A= 1
C= 0
0
B= 1
C= 0
0
0
1
F1
0
0
1
F2
A
0
0
0
0
1
1
1
11
B
0
0
1
1
0
0
1
C
0
1
0
1
0
1
0
F1
0
1
1
0
1
0
0
F2
0
0
0
1
0
1
1
Analysis Procedure
• Truth Table Approach
A= 1
B= 1
C= 1
A= 1
B= 1
C= 1
1
1
1
F1
0
0
A= 1
B= 1
1
A= 1
C= 1
1
B= 1
C= 1
1
1
F2
12
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
B
A
F1
0
1
1
0
1
0
0
1
C
0
1
0
1
0
1
0
1
B
0
1
0
1
1
0
1
0
C
F1=AB'C'+A'BC'+A'B'C+ABC
A
0
0
1
0
0
1
1
1
C
F2=AB+AC+BC
F2
0
0
0
1
0
1
1
1
Design Procedure
• Given a problem statement:
– Determine the number of inputs and outputs
– Derive the truth table
– Simplify the Boolean expression for each
output
– Produce the required circuit
Example:
Design a security alarm circuit:
?
13
Design Example
• Design a circuit to convert a
“BCD” code to “Excess 3” code
14
Design Example
15
• BCD-to-Excess 3 Converter
C
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
w
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x
x
0
1
1
1
1
0
0
0
0
1
x
x
x
x
x
x
y
1
0
0
1
1
0
0
1
1
0
x
x
x
x
x
x
z
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
A
x
1
1
x
1
1
x
x
1
x
x
C
B
A
1
x
1
1
1
x
1
x
x
x
x
D
D
w = A+BC+BD
x = B’C+B’D+BC’D’
C
A
1
1
x
1
1
1
x
x
x
B
C
x
x
B
A
1
1
x
1
D
y = C’D’+CD
x
x
x
D
z = D’
1
1
x
x
B
Design Procedure
16
• BCD-to-Excess 3 Converter
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
w
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x
x
0
1
1
1
1
0
0
0
0
1
x
x
x
x
x
x
y
1
0
0
1
1
0
0
1
1
0
x
x
x
x
x
x
z
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
A
w
x
B
C
y
D
z
w = A + B(C+D)
x = B’(C+D) + B(C+D)’
y = (C+D)’ + CD
z = D’
More Blocks: Binary Adders
• Half Adders: adds 2 1-bit operands (x and y)
to produce 2-bit result (a carry and a sum)
Sum = S = a’b+ab’ = ab
Carry = C = ab
17
Half Adders
• Example: built a four bit adder using Half
adders only.
• Half adders doesn’t consider the previous
carry => need to include carry-in
18
Full Adders
• Carry is included as another input => 3 inputs
and 2 outputs:
ab
Cin
SUM
00 01 11 10
0 0
1
1
3
1 41 5
ab
Cin
7
2
1
1
6
Cout
00 01 11 10
0 0
1 4
1
3
1
5
1 71
2
6
1
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Full Adders
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• 1-bit Full adder:
S = abCin
Cout = a b+a Cin+b Cin
• 4-bit full adder: 4 cascaded (connecting one
after the other) full adders, called ripple adder.
Ripple Adder
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• The carry has to propagate (ripple) through all
adders,
• Next adder has to wait for carry-in from
previous adder, delay of two gates (AND-OR)
per adder => 4-bit adder => 8 gate delay.
• What about 64-bit adder => 128 gate delay=>
delay is too high.
• Ripple adder rarely used.
Carry Look Ahead Adder
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• Attempt to generate the carry-in using a separate
logic, eliminate waiting time (does not wait for the
previous adder to generate the carry).
• Carry Generate: for a particular combination of
inputs ai and bi, adder stage i is said to generate a
carry if it produces carry-out of 1 (ci+1=1)
independent of the inputs a0-ai-1, b0-bi-1, and c0
• Carry Propagate: for a particular combination of
inputs ai and bi, adder stage i is said to propagate
carries if it produces carry-out of 1 (ci+1=1) in the
presence of the input combination a0-ai-1, b0-bi-1, and
c0 that causes a carry-in of 1 (ci=1)
Carry Look Ahead Adder
23
• To realize the propagate and generate cases,
we introduce two functions as shown:
• Back to the carry equation:
Ci+1 = (ai.bi)+(ai+bi).Ci = gi + pi .Ci
generate propagate
a
b
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Cin Cout S G
0 0 0 0
1 0 1 0
0 0 1 0
1 1 0 0
0 0 1 0
1 1 0 0
0 1 0 1
1 1 1 1
P.Cin
0
0
0
1
0
1
0
1
Carry Look Ahead Adder
Ci+1 = (ai.bi)+(ai+bi).Ci = gi + pi .Ci =>
Stage 0: C1 = g0 + p0 .C0 = (a0.b0)+(a0+b0).C0
Stage 1: C2 = g1 + p1 .C1 = (a1.b1)+(a1+b1).C1
=g1+p1.g0+p1. p0.C0
Stage 2: C3 = g2 + p2 .C2 =g2 + p2 .(g1 + p1 .C1 )
= g2+p2g1+ p2p1g0 + p2p1p0 .C0
Stage 3: C4 = g3 + p3 .C3 =g3 + p3 .(g2 + p2 .C2 )
= g3 + p3 .(g2 + p2 .(g1 + p1 .(g0 + p0 .C0) ))
= g3+ p3g2 +p3p2g1+p3p2p1g0+p3p2p1p0C0
24
Carry Look Ahead Adder
25
• Basically we will add a separate hardware to
break up dependency between sum and carry
=> duplicating logic area
• Still suffer from gates with large number of
inputs => increasing Fan-In (more inputs) =>
larger transistors => higher power
consumption and slower.
Ripple Carry and CLA
26
CLA
27
CLA Adders
• Use a combination of CLA Adders and Ripple
Adders,
• Optimization between delay, power and area can
take place here to find the optimal size of the CLA
Adders.
28
Cascaded CLA Adders
• Example: 16-bit Adder, then cascade 4 CLA
Adders of 4-bit size.
29
Binary Subtractor
30
• Use 2’s complement with binary adder
– x – y = x + (-y) = x + y’ + 1
x3 x2 x1 x0
y3
y2
y1
y0
A3 A2 A1 A0 B3 B2 B1
Cy
Binary Adder
S3 S2 S1 S0
B0
Ci
F3 F2 F1 F0
1
Adder/Subtractor
• The M signal has to be 1 when subtraction
operation is needed and 0 if addition is
needed:
31
BCD Adder
• 4-bits plus 4-bits
• Operands and Result: 0 to 9
X +Y x3 x2 x1 x0
0+0 0 0 0 0
0+1 0 0 0 0
0+2 0 0 0 0
y3 y2 y1 y0 Sum
0 0 0 0 =0
0 0 0 1 =1
0 0 1 0 =2
0+9
1+0
1+1
0 0 0 0
0 0 0 1
0 0 0 1
1 0 0 1
0 0 0 0
0 0 0 1
=9
=1
=2
1+8
1+9
2+0
0 0 0 1
0 0 0 1
0 0 1 0
1 0 0 0
1 0 0 1
0 0 0 0
9+9
1 0 0 1
Cy
0
0
0
S3 S2 S1 S0
0 0 0 0
0 0 0 1
0 0 1 0
0
0
0
1 0 0 1
0 0 0 1
0 0 1 0
=9 0
=A 0
=2 0
1 0 0 1
1 0 1 0
0 0 1 0
1 0 0 1 = 12 1
0 0 1 0
0001 1000
32
+ x3 x2 x1 x0
+ y3 y2 y1 y0
────────
Cy S3 S2 S1 S0
Invalid Code
Wrong BCD Value
BCD Adder
33
X +Y
x3 x2 x1 x0
y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value
9+0
9+1
9+2
9+3
9+4
9+5
9+6
9+7
9+8
9+9
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
=9
= 10
= 11
= 12
= 13
= 14
= 15
= 16
= 17
= 18
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
+6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
=9
= 16
= 17
= 18
= 19
= 20
= 21
= 22
= 23
= 24









BCD Adder
34
• Correct Binary Adder’s Output (+6)
– If the result is between ‘A’ and ‘F’
– If Cy = 1
S3 S2 S1 S0
0 0 0 0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Err
0
0
0
1
1
1
1
1
1
S1
S3
1
1
1
1
1
1
S2
S0
Err = S3 S2 + S3 S1
BCD Adder
x3 x2 x1 x0
y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0
Err
0
0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0
Cy
S3 S2 S1 S0
35
0
0
Overflow
36
• Unsigned Binary xNumbers
x
3
x1
2
y3
y2
x0
y0
y1
0
FA
Carry
C4
FA
S3
C3
FA
S2
• 2’s Complement Numbers
x3
C2
x2
y3
S1
FA
C1
x1
y2
S0
x0
y0
y1
0
FA
Overflow
C4
FA
S3
C3
FA
S2
C2
S1
FA
C1
S0
37
 Binary Multiplier
● Two 2-bit numbers (A=A1 A0) and (B=B1 B0) .
X0
X1
X3
X0
X2
X3
X2
X1
38
 Binary Multiplier
● Two binary numbers :
● J multiplier bits
● K multiplicand bits.
 We need:
● (J  K) AND gates.
● (J 1) K-bit adders
39
 Binary Multiplier
J=3
K=4
AND gates (12 gates)
B3
B2
B1
B0

A2
A0
A1
_________________________________
0
A0B3
A0B2
A0B1
A0B0
4-bit Adder (2 units)
+
A1B3
A1B2
A1B1
A1B0
_____________________________________
Z1
Z0
Z2
Z4
Z3
+
A2B0
A2B1
A2B3
A2B2
__________________________________________________
C6
C5
C4
C3
C2
C1
C0
40
 Binary Multiplier
B3
B2
B1
B0

A2
A0
A1
_________________________________
0
A0B3
A0B2
A0B1
A0B0
+
A1B3
A1B2
A1B1
A1B0
_______________________________
Z1
Z0
Z2
Z4
Z3
+
A2B0
A2B1
A2B3
A2B2
__________________________________________________
C6
C5
C4
C3
C2
C1
C0
Z4 Z3 Z2 Z1
Z0
Decoders and Encoders
41
• A code is a string of several bits, with an n-bit code, it
is possible to represent 2n. A decoder translate the nbit pattern into a specific code of 2n possible values.
• A decoder translate a binary value into a non-binary
output.
• An encoder, translate a non-binary value into a
binary value.
• An n-input decoder has n-inputs and 2n outputs
Decoders
42
• One-hot encoding (only one output high at a time)
• Example: a 3-bit binary to decimal decoder, called 3to-8 decoder.
Functions using Decoders
43
• We can implement functions using decoders.
• Example: F(A,B,C) = Σm(1,3,7) and
G(A,B,C) = Σm(2,3,6) using decoder
• Less efficient than our optimized AND-OR
logic, but sometimes used in small circuits
(MSI).
Decoder-Based Adder
• One decoder to implement a full adder with
sum and carry output.
• C = Σm(3,5,6,7) and S =Σm(1,2,4,7)
44
Code Conversion
•
•
-
Decoders are also used for code conversion,
Example code conversion can be:
BCD-to-7 segment display
BCD-to-decimal
BCD-to-Gray
Binary-to-Gray
45
BCD-to-7 segment display
• Example
46
Cascading Decoders
•
•
•
•
3-to-8 decoder requires 8 gates
4-t0-16 requires 16 gates
5-to-32 requires 32 gates
Number of gates increases exponentially with
number of inputs.
• You might not need all outputs (BCD-todecimal)
• Cascade decoders and use only the required
number of outputs
47
Building 3-8 out of 2-4 Decoders
48
• Another way to design a decoder is to break it into
smaller decoders:
– When S2 = 0, outputs Q0-Q3 are generated as in
a 2-to-4 decoder.
– When S2 = 1, outputs Q4-Q7 are generated as in
a 2-to-4 decoder.
S2
S1
S0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
= S2’ S1’ S0’
= S2’ S1’ S0
= S2’ S1 S0’
= S2’ S1 S0
= S2 S1’ S0’
= S2 S1’ S0
= S2 S1 S0’
= S2 S1 S0
= m0
= m1
= m2
= m3
= m4
= m5
= m6
= m7
3-8 Decoder
49
• Enable input used to select lower or higher
nibble:
S2
S1
S0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Cascading Decoders
• 4-to-16 decoder made of 2x 3-to-8 decoders
50
Active-Low Decoder
• So far we looked at active high decoders.
• Active-low decoders are similar but with
inverted input and outputs
EN
S1
S0
Q0
Q1
Q2
Q3
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
x
x
1
1
1
1
51
Active Low Decoders
52
• An active low 2-to-4 decoder with enable,
• Active Low => use Maxterms:
D0= E+A+B =(E’.A’.B’)’; D1= E+A+B’ =(E’.A’.B)’;
D2= E+A’+B =(E’.A.B’)’; D3= E+A’+B’ =(E’.A.B)’;
Using NAND will convert Maxterms to minterms
Active Low Decoders
• Active-low decoders generate Maxterms
Q3’= (S1 S0)’ = S1’ + S0’
Q2’= (S1 S0’)’ = S1’ + S0
Q1’= (S1’ S0)’ = S1 + S0’
Q0’= (S1’ S0’)’ = S1 + S0
• Example: f(x,y,z)= ΠM(4,5,7)
• Use a NAND to generate minterms
53
Encoders
54
• An encoder performs the reverse function of a
decoder => has fewer outputs to inputs.
• A binary encoder has 2n-n input to output.
• Usually only one input is 1 the rest is zero.
Example: 8-to-3 Encoder
• Only one input at a time is high, the rest is
zero,
Idle = I7’. I6’. I5’. I4’. I3’. I2’. I1’. I0’
Valid = I7+ I6+ I5+ I4+ I3+ I2+ I1+ I0
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
000 00001 0 0 0
000 00010 0 0 1
000 00100 0 1 0
000 01000 0 1 1
000 10000 1 0 0
001 00000 1 0 1
010 00000 1 1 0
100 00000 1 1 1
000 00000 x x x
Idle Valid
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
55
Priority Encoders
56
• The assumption of having a single input as a one
and the rest are zeros might be violated (sending
multiple interrupt requests to the encoder in a microprocessor).
• Example: I2 and I4 are one which it will produce
Y2Y1Y0 = 110 (it should’ve been either 010 or 100)
• Priority encoder ensures this never happen by
assigning priority to the input lines.
• Thus, if more than one input is high, the encoder
produces the proper binary output associated with
the input that has the highest priority.
Priority Encoders
• Introduce an intermediate function H’s:
I7 I6 I5 I4 I3 I2 I1 I0 H7 H6 H5 H4 H3 H2 H1 H0
000 00000 0 0 0 0 0 0 0 0
1x x xxxx x 1 0 0 0 0 0 0 0
01x xxxx x 0 1 0 0 0 0 0 0
001 xxxx x 0 0 1 0 0 0 0 0
000 1xxx x 0 0 0 1 0 0 0 0
000 01xx x 0 0 0 0 1 0 0 0
000 001x x 0 0 0 0 0 1 0 0
000 0001x 0 0 0 0 0 0 1 0
000 00001 0 0 0 0 0 0 0 1
A2 A1 A0
x x x
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
Idle
1
0
0
0
0
0
0
0
0
57
Priority Encoder
• Example:
I7I6I5I4I3I2I1I0 = 00100100 => I5 is higher priority
than I2 =>
H7H6H5H4H3H2H1H0 = 00100000 =>
A2A1A0 = 101
58
Multiplexers: Data Selector
• Multiplex the inputs and pass one or more
signal to the output using a selector.
• 2n inputs to one output with n selectors.
n 1
Y   m j .X j
j 0
59
Multiplexers
60
• 4-to-1 Multiplexer:
Y = S1’.S0’.X0+ S1’.S0.X1+S1 .S0’.X2+S1 .S0.X3
S1 S0
Y
0
0
1
1
X0
X1
X2
X3
0
1
0
1
4-ways Multiplexer
61
• Output = Minterm . Input
• Out = m0.W+m1.X+m2.Y+m3.Z
• Out = S1’.S0’.W+S1’.S0.X+S1.S0’.Y+S1.S0.Z
S1 S0 out
0
0
1
1
0
1
0
1
W
X
Y
Z
Bus Multiplexing
• Multiplexing a bus of MxN data lines into N
data lines.
• Needs M selectors
• Output Bus A or Bus B
• Each bus is 4-bit wide
62
Build Multiplexers Using Decoders
• Use a decoder to generate the minterms
63
Building Logic Functions Using MUXs
64
• The variables has to be split into inputs and
selectors of the multiplexer.
• A common way to use n-1 as selectors and
the remaining variable with its complement as
an input.
• Example: given the function:
F(A,B,C) = Σm(2,3,5,7)
To be implemented using 8-to-1 multiplexer
Building Logic Functions Using MUXs
• F(A,B,C) = Σm(2,3,5,7)
65
Building Logic Functions Using MUXs
• F(A,B,C) = Σm(2,3,5,7)
• Using 4-to-1 MUX
66
67
Building Logic Functions Using MUXs
•
•
•
•
Example:
F(A,B,C) = Σm(1,3,5,6)
Can you use 4-to-1 MUX?
2 variables as selectors
Building Logic Functions Using MUXs
• Example: implement the following function
using 8-to-1 MUX:
F(A, B, C, D)  m(0,1,3,6,7,8,11,12,14)
• 4-to-1 MUX?
F(A,B,C,D)  m(0,1,3,4,8,9,15)

68
Designing Using MUXs
69
• Design an Adder/ Subtractor using MUXs and
a single Adder to that can do the following
operations: A-B, -A+B, B-A, -B+A
Demultiplexer
70
• One input to 2n outputs with n selectors
Y0 = S1’.S0’.X
Y1 = S1’.S0.X
Y2 = S1 .S0’.X
Y3 = S1 .S0.X
similar to decoders?
S1 S0 Y0 Y1 Y2 Y3
0
0
1
1
0
1
0
1
X
0
0
0
0
X
0
0
0
0
X
0
0
0
0
X
Tri-State Buffer
• A Tri-state buffer can output either 1, 0, or
high impedance.
71
Comparators
• Inputs A and B each of n-bits
• Output is 1 if A=B A>B A<B and 0 if A≠B
A0 B0 A0=B0
0
0
1
1
0
1
0
1
1
0
0
1
72
Comparators
• Output 1 if A> B and 0 otherwise
A0 B0 A0>B0
0
0
1
1
0
1
0
1
0
0
1
0
73