Transcript History of the MOSFET

History of the MOSFET? What’s that?
 Thanks to Jiseok Kim for having put me on the spot….
It’s OK… I wish him good luck in getting his PhD wherever ELSE he may wish to get it….
 I’m not sure what he meant by “history”… So, let’s start from the beginning….
MVF October 2, 2009
1
The main character of our story: The MOSFET
 No other human artifact has been fabricated in larger numbers (except perhaps nails?)
 “…some consider it one of the most important technological breakthroughs in human
history…” (Wikipedia, the source of all human knowledge)
MVF October 2, 2009
2
Timeline I
Technology
Physics/Simulations
1925: Julius Edgar Lilienfeld’s MESFET patent
1935: Oskar Heil’s MOSFET patent
194?: Unpublished Bell Labs MESFET
1947: Ge BJT (Bardeen, Brattain, Shockley, Bell Labs)
1954: Si BJT (Teal, Bell Labs)
1955: Si, Ge conduction band (Herring&Vogt)
1960: MOSFET (Atalla&Khang, Bell Labs)
Deformation-potential, high-field (Bardeen&Shockley)
1961: Integrated circuit (Kilby, TI)
1957: BTE in semiconductors – impurities (Luttinger&Kohn),
1963: CMOS (Sah&Wanlass, Fairchild)
phonons (Price, Argyles)
1964: Commercial CMOS IC (RCA)
1964: Band structure calculations (Hermann)
1965: DRAM (Fairchild)
Monte Carlo for semiconductors (Kurosawa)
1968: Poly-Si gate (Faggin&Klein, Fairchild)
1965: Linear-parabolic oxidation model (Deal&Grove)
1968: 1-FET DRAM cell (Dennard, IBM)
1966: Observations of 2DEG (Fowler, Fang, Stiles, Stern,..)
1971: UV EPROM (Frohman, Intel)
1967: Conductance technique (Nicollian&Goetzberger)
1971: Full CPU in chip, Intel 8008 (Faggin, Intel)
1974: Digital watch
1974: DDE device simulator (Cottrell&Buturla)
1974: Scaling theory (Gänsslen&Dennard, IBM)
1975: Quantum Hall Effect predicted (Ando)
1978: Use of ion implanter
1978: Flotox EEPROM (Perlegos, Intel)
1979: Quantum Hall Effect observed (von Klitzing)
1980: Ion-implanted CMOS IC
1981: Identification of native Nit: Pb-centers (Poindexter)
1980: Plasma etching
Full-band MC (Shichijo&Hess)
1984: Scaling theory <0.25 μm (Baccarani, U. Bologna)1982: Fractional QHE observed (Störmer&Tsui, Laughlin)
1986: 0.1 μm Si MOSFET (Sai-Halasz, IBM)
1988: Full-band MC device simulator (MVF&Laux)
1991: CMOS replaces BJT also at high-end
1992: NEGF device simulator (Lake, Klimeck, et al.)
1993: DGFET scalable to 30 nm (theory, Frank et al.)
2007: Non-SiO2 (HfO2–based) MOSFET (Intel)
MVF October 2, 2009
3
Timeline II
Feature size
1975: 20 μm (tOX≈250 nm)
Main Problems
↑
SiO2 growth and instability: Ions, traps, interface
1980: 10 μm (tOX≈150 nm)
1985: 5 μm (tOX≈70 nm)
SiO2 instability during operation: electron trapping, NBTI
Hot electron effects: oxide trapping, VT shift, breakdown
1990: 1 μm (tOX≈15 nm)
Scaling: Short-channel effects (SCE), oxide, dopants
↓
1995: 0.35 μm (tOX≈8 nm)
2000: 0.18 μm (tOX≈3 nm)
….life is good…
2005: 65 nm (tOX≈1.4 nm)
2010: 32 nm (tOX≈1.2 nm?)
MVF October 2, 2009
Scaling: SCE, insulator
Leakage: Insulator
Power: Alternative devices
4
Timeline III
Feature size
Transport Physics
1975: 20 μm
1980: 10 μm
1985: 5 μm
Drift-Diffusion
↓
Hydrodynamic/
Energy transport
1990: 1 μm
1995: 0.5 μm
2000: 0.25 μm
2005: 63 nm
2010: 32 nm
2015: 16 nm ?
MVF October 2, 2009
↕
Boltzmann
↓
Quantum?
5
Transistor prehistory
1935 Heil’s patent
MVF October 2, 2009
1947 First BJT
1960 Atalla’s MOSFET
Bardeen, Shockley, Brattain (Bell Labs)
6
IC Prehistory
1961 Kilby’s first IC
MVF October 2, 2009
1962 Fairchild IC
1964 First MOS IC
(RCA)
7
Moore’s law prehistory
Gordon Moore
MVF October 2, 2009
1965: Cost vs time
Moore’s law 1960-1975
8
Moore’s law
Number of transistors/die & feature size vs time
MVF October 2, 2009
9
Microprocessor prehistory
1965: Federico Faggin
MVF October 2, 2009
1968: Fairchild 8-bit μP
1971: Intel 8080 μP
10
Memory prehistory: DRAM and EPROM
Bob Dennard (1-FET DRAM cell, 1968;
scaling theory with Fritz Gänsslen,1974)
MVF October 2, 2009
1971 Frohman’s UV-erasable EPROM
(written by avalanche injection)
11
More historical trends
MVF October 2, 2009
J. Armstrong (ca.1989)
12
Timeline II once more
Feature size
1975: 20 μm (tOX≈250 nm)
Main Problems
↑
SiO2 growth and instability: Ions, traps, interface
1980: 10 μm (tOX≈150 nm)
1985: 5 μm (tOX≈70 nm)
1990: 1 μm (tOX≈15 nm)
SiO2 instability during operation: electron trapping, NBTI
Hot electron effects: oxide trapping, VT shift, breakdown
Scaling: Short-channel effects (SCE), oxide, dopants
↓
1995: 0.35 μm (tOX≈8 nm)
2000: 0.18 μm (tOX≈3 nm)
….life is good…
2005: 65 nm (tOX≈1.4 nm)
2010: 32 nm (tOX≈1.2 nm?)
MVF October 2, 2009
Scaling: SCE, insulator
Leakage: Insulator
Power: Alternative devices
13
SiO2 growth and instability
 Ionic contamination (K, Na): Unrecognized source of early problems
 Fixed traps (oxygen vacancies?), especially near Si-SiO2 interface
 Growth kinetics: Deal & Grove model: linear (reaction-limited) and parabolic (diffusion-limited)
regions; dry and wet oxidation rates
 Interface-state passivation: Al (with H) Post Metallization Anneal (PMA, Peter Balk):
 H2O → H+ + OH Si- + H+ → Si-H
Andrew Grove (left), Bruce Deal (center)
and Ed Snow (left)
MVF October 2, 2009
Ed Snow’s cartoon, ca. 1966
about SiO2 instabilities
14
SiO2 growth and instability, as-grown and during operation
 CV-plot instabilities (VFB or VT shifts):
 Ions (mainly Na+ and K+, contamination in chambers, handling, gases, etc…)
 Interface states generation (stretch-out, Lai, Feigl, Sandia group, Technion, Siemens,…)
 Electron and hole traps (DiMaria, Young, Feigl):
• Neutral: H2O-related (mainly OH-) in wet oxides, radiation induced in processing,
σ ≈ 10-15 to 10-17 cm2
• Charged-attractive: Ionic contamination, σ ≈ 10-13 cm2 , field-dependent
• Charged-repulsive: Radiation-induced, σ ≈ 10-19 cm2
MVF October 2, 2009
15
SiO2 instability during operation
 Anomalous Positive Charge (APC):
 Caused by electron injection (Avalanche, Fowler-Nordheim) and also hole injection
 Related to Hydrogen: Boron deactivation in p-type substrates (Sah)
 Related to hole back-injection from anode? Dependent on gate-metal workfunction Au vs. Al vs. Mg (MVF&Weinberg, Chenming Hu)
 Occurring at Si-SiO2 interface even under negative bias: Neutral species such as
solitons, H2 diffusion…? (Weinberg).
 Connected to wear-out and breakdown (DiMaria, Stathis)
 Strongly correlated to interface traps (Pb-centers, Lenahan, Poindexter)
 Oxygen deficiency (Revesz)? Broken Si-H bonds (Si-D experiment, Lyding&Hess)?
 Negative Bias Temperature Instability (NBTI): No time to discuss, but big issue in high-κ
dielectrics
MVF October 2, 2009
16
Understanding SiO2 degradation: Two approaches
MVF and DiMaria, INFOS 1989
MVF October 2, 2009
17
SiO2 growth and instability: Injection techniques and damage generation
MVF October 2, 2009
18
SiO2 growth and instability: Electronic transport in SiO2
 Electrons:
 Long-standing problems of high-field electron transport in polar insulators
(Karel Thornber’s 1970 PhD Thesis with Richard Feynman)
 LO-phonon scattering run-away connected to dielectric breakdown
 Experimental observations do not show predicted run-away at 2-3 MV/cm
 Umklapp scattering with acoustic phonons keeps electron energy under
control (MVF, DiMaria, Theis, Kirtley, Brorson, 1985)
 Holes: Small polaron (self-trapping) transport (Bob Hughes’ 1977 time-of-flight
experiments explained by David Emin’s 1975 theory).
MVF et al., PR B (1985)
MVF October 2, 2009
19
Hot electron effects in constant-voltage-scaled MOSFETs
 Two problems:
 Understand origin/spectrum of hot carrier
 Understand nature/process of damage generation
 Practical problems:
 Unnecessary and expensive burn-in
 Wall Street “big glitch” in 1994
 Theory:
 Shockley’s “lucky-electron model” widespread in EE community in the ’80s
(publicized by Chenming Hu, UCB): Even the Gods can be wrong at times…
 Full-band models (Sam Shichijo & Karl Hess, MVF&Laux, then others)
 Basic physics of electron scattering, injection into SiO2, etc.
 The mid-1990s “pseudo-full-band” frenzy (Bologna, UNC, Udine, Lille, TUVienna, Aachen,..): Gain without pain… didn’t work…
MVF October 2, 2009
20
Electron injection into SiO2
MVF, Laux, and Crabbé, JAP (1996)
MVF October 2, 2009
21
Timeline III once more
Feature size
Transport Physics
1975: 20 μm
1980: 10 μm
1985: 5 μm
Drift-Diffusion
↓
Hydrodynamic/
Energy transport
1990: 1 μm
1995: 0.5 μm
2000: 0.23 μm
2005: 63 nm
2010: 32 nm
2015: 16 nm ?
MVF October 2, 2009
↕
Boltzmann
↓
Quantum?
22
Electron transport in Si at 3 eV: A big headache
 Effective-mass approximation valid only for E ≈ a few kBT
 Scattering rates at E ≥ {a few kBT} totally unknown
 Moments of the BTE (DDE, Hydrodynamic) not sufficiently accurate
MVF October 2, 2009
23
Electron transport in Si at 3 eV ca. 1992: A depressing picture…
The state-of-the art circa 1992
MVF October 2, 2009
24
A good example of experiments-theory feedback
XPS (McFeely, Cartier, Eklund at the
Brookhaven IBM synchrotron line, 1993)
Carrier separation (DiMaria, 1992)
Cartier et al. APL (1993)
MVF October 2, 2009
25
Electron transport in Si at 3 eV ca. 1994: Much better…
The state-of-the art circa 1994
MVF October 2, 2009
MVF et al., JAP (1996)
26
Scaling
 Shrink dimensions maintaining aspect-ratio
 Must shrink electrostatic features as well (depletion regions→ doping level and profiles)
↔
1 μm
1980 → 1985 → 1988 → 1991 → 1994
1994 → 1999 → 2003 …
μm 1.3
nm ….
LGATE
μm 2.5
2.5 μm
1.3 μm
μm 0.63
0.63 μm
μm 0.25
0.25 μm
μm 130
130 nm
nm
….
5 μm
GATE = 10 μm
MVF October 2, 2009
27
Scaling




Electrostatic integrity (Well-tempered MOSFET, Antoniadis): SOI, DGFETs, FinFETs, NW-FETs
Reduce power, an example: The tunnel FET n (tFET)
Reduced leakage: High-κ gate-insulators
Improve (or, at least, maintain) performance: Alternative channel materials?
MVF October 2, 2009
28
Scaling – Electrostatic integrity: SOI
22 nm strained-Si nFET: SOI to prevent punch- through,
strained Si to improve performance (B. Doris, IBM, 2006)
MVF October 2, 2009
29
Scaling – Electrostatic integrity: Double gate FET
AIST (2003)
MVF October 2, 2009
30
Scaling – Electrostatic integrity: Multibridge FETs (TEM, SEM)
Samsung Electronics Ltd. (2005)
MVF October 2, 2009
31
Multibridge FETs: Process flow
Samsung Electronics Ltd. (2005)
MVF October 2, 2009
32
Scaling – Electrostatic integrity: FinFETs
Freescale Semiconductors
MVF October 2, 2009
33
Scaling – Electrostatic integrity: Si Nanowire Transistors
KAIST (2007)
MVF October 2, 2009
34
Scaling – Reduce power: The tunnel-FET (tFET)

Stand-by power dissipation approaching “on”
power dissipation… Cannot continue like this!

60 mV/dec → ΔVG ≈ 250 mV for Ioff/Ion ≈ 10-4

VT + ΔVG ≥ 0.45 V at 300 K (nFETs)
Must increase slope (i.e., go below 60 mV/dec) if
we want the `Green’ FET (term coined by C. Hu)
Problem: Ion too low in all attempts (DARPA to
IBM, UCB, Stanford,…) so far


InAs Tunnel-FET: structure
(M. Haines, UMass 2009)
MVF October 2, 2009
InAs Tunnel-FET: pair generation rate
(M. Haines, UMass 2009)
35
Scaling – Reduce leakage
 Off-leakage:
 Accepted value increasing: Ioff/Ion ≈ 10-4 for the 32 nm node (used to be 10-6 or lower!)
 Connected to electrostatic integrity (punch-through, junction leakage, gate leakage)
 Gate leakage:
 C = εox/tox, so if tox has reached its limit (≈ 1nm, too aggressive so far), scale εox:
High-κ insulators such as HfO2, ZrO2, Al2O3, etc.
 Problem: Low mobility in high-κ MOS systems (scattering with interfacial optical phonons)
 Metals with different workfunction needed!
Hi-res TEM from
Susanne Stemmer,
UCSB
MVF October 2, 2009
MVF et al., JAP (2001)
36
Scaling – Reduce leakage: Gate oxide scaling at Intel
MVF October 2, 2009
C. Hu et al., IEDM (1996)
37
Scaling – Improve performance
 Taken for granted early on (ca. 1986)
 Slow realization that early optimism was unjustified
MVF and S. Laux, EDL (1987)
MVF October 2, 2009
38
Scaling – Improve performance
 Look for high-velocity, low-effective mass semiconductors… or should we?
 Problems:
 High-energy (≈ 0.5 eV ≈ 20 kBT) DOS and rates identical in most fcc semiconductors
 Low DOS → loss of transconductance
 Low DOS → smaller density in quasi-ballistic conditions → lower Ion
 Low DOS → less scattering in source → source starvation
MVF October 2, 2009
39
Scaling – Improve performance: DOS bottleneck
MVF October 2, 2009
MVF and S. Laux, TED (1991)
40
Scaling – Improve performance: Strained Si
MVF October 2, 2009
MVF and S. Laux, JAP (1996)
41
Scaling – Improve performance: Strained Si
IBM 32 nm strained (tensile)
Si nFET on SiGe virtual substrate
MVF October 2, 2009
Intel 45 nm strained (compressive)
Si pFET with regrown SiGe S/D
42
Why are sub-40 nm devices getting slower?
 Power dissipation → reduce frequency or fry!
 Parasitics play a bigger role (Antoniadis, MIT)
 Higher oxide fields squeeze carriers against interface → increased scattering
(Antoniadis, MIT)
 Intrinsic Coulomb effects!
MVF and S. Laux, JAP (2001)
MVF October 2, 2009
43
Why are sub-40 nm devices getting slower? The effect of e-e interactions
MVF October 2, 2009
44
Sub-32 nm Si CMOS devices: Where do we stand?
 22 nm: Planar (Intel), SOIs (IBM), FinFETs doable but too expensive.
 16 nm: Possibly FinFETs, still Si
 Below 16 nm:
 Ge pFETs and III-V nFETs (IMEC)? A pipedream…
 Ge nFETs still lousy, improvements promised at Dec 2009 IEDM, we’ll see
 III-Vs in the works:
• MIT (del Alamo): Great HEMTs, but huge S/D-gate gap not easily scalable
• SRC/UCSB MOSFETs: Wait and see…
MVF October 2, 2009
45
The future and “post Si CMOS” devices: What do we need?
Three terminal devices (Josephson computers taught us something…!)
At least some gain (preserving signal over billions of devices, beating kBT)
At least a few devices must have high Ion to charge external loads
On/off behavior (Landauer’s water faucet analogy)
Low power, possibly non-charge-switching (spins, QCA,…). BUT: If we use ≈ kBT to
switch, the heat bath will switch for us even if we do not want to…
 Notable historic failures:
 Josephson: Excessively strict tolerances (on insulators), complicated 2-terminal logic
 SETs: No output current (`a slight impedance matching issue’, as someone kindly put
it….)
 Optical computers: Photons are huge! Clumsy 3-terminal devices
 Resonant tunneling diodes and multi-state logic: Non off-off switches, impossible to
control manufacturing tolerances
 High hopes:
 Nanowires: They are just thin and narrow FinFETs
 Long shots:
 Spins and QCA: Low power but no gain
 CNT: No current in single tube, must use many in parallel
 III-Vs: Battle already lost in 1991 (DOS bottleneck),,, why bother again?





MVF October 2, 2009
46
And by popular demand… The future of “post-Si CMOS” logic technology
MVF October 2, 2009
47
More slides about the lunatic fringe….
MVF October 2, 2009
48
The lunatic fringe: Exploratory devices
MVF October 2, 2009
49
The lunatic fringe: Exploratory devices
MVF October 2, 2009
50
The lunatic fringe: Exploratory devices
Carbon NanoTube (CNT) FET
IFF-Jülich, Germany (2004)
MVF October 2, 2009
51
CNT Transistors
IFF-Jülich, Germany (2004)
MVF October 2, 2009
52
CNT FET inverter
J. Appenzeller, IBM
MVF October 2, 2009
53