Transcript 2 - indico in2p3

CSNSM
Orsay Micro-Electronics
Groups Associated
P. Barrillon, S. Blin, S. Callier, S. Conforti, F.
Dulucq, J. Fleury, C. de La Taille, G. MartinChassard, L. Raux, N. Seguin-Moreau, V. Tocut
+ Xiongbo Yan from IHEP Beijing
Microelectronics at in2p3
• Large force of microelectronics experienced
engineers (~40)
• Expertise in detectors, chip design and test
• Experience in designing and building large detectors
• Common Cadence tools
• Actions :
– Building blocks
– Networking
– poles
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Motivation for poles
• Continuous increase of chip complexity (SoC, 3D…)
• Importance of critical mass
– Daily contacts and discussions between designers
– Sharing of well proven blocks
– Cross fertilization of different projects
• Creation of poles at in2p3
– OMEGA at Orsay
– Strasbourg
– Dipole Lyon-Clermont
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Club building blocks 0.35µm
• Mission
Design of basic building blocks usable by all in2p3
labs for physics experiments
• Motivations
– Target analog technology (0.35µm CMOS and SiGe AMS )
– Optimize ressources and competences within in2p3
– Increase visibility of in2p3 in microelectronics
– reduce developpement times
• First results
– 2-3 runs /yr financed by in2p3
– Porquerolles workshop
– Fruitful exchanges
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New club 130nm for tracking and 3D
• Networking : club 130nm created at VLSI workshop
– Target common technology with CERN or other labs : IBM
130nm with CERN, Chartered 130nm (IBM compatible)
• 3D consortium : CPPM, IPHC, OMEGA, LPNHE
– Complementarity
– Task sharing
– Coordination
• IN2P3 Recommendation : participate to 3D effort in
a coherent, coordinated and funded way.
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Orsay Micro-Electronics Groups Associated
• A strong team of 10 ASIC designers…
– = 20% of in2p3 designers
– = 60% of department research engineers
– A team with critical mass : pole created in
2007 = OMEGA
– Expertise in low noise, low power high level
of integration ASICs
– 2 designers/ project
– 2 projects/designer
– Regular design meetings
ASPIC
HARDROC
• …Within an electronics departmt of 50
MAROC 2
SKIROC
– Support for tests, mesaurements, PCBs…
• A steady production
– A strong on-going R&D
– Building blocks SiGe 0.35µm
SPIROC
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Orsay micro-electronics team
•
•
•
•
8
1
1
1
research engineers (1 IR0, 2 IR1, 5 IR2)
CDD IR2 EUDET
phD student
visitor from China IHEP Beijing
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Recent chips
• Several chips developped for ATLAS LAr, OPERA, LHCb, CALICE
in BiCMOS 0.8µm and installed on experiments
• Turn to Silicon Germanium 0.35 µm SiGe BiCMOS technology in
2005
• Readout for MaPMT and ILC calorimeters
• Very high level of integration : System on Chip (SoC)
• Parallel activity of building blocks
ASPIC MAROC 2
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HARDROC
SKIROC
SPIROC
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MAROC : 64 ch MAPMT chip for ATLAS lumi
Complete front-end chip for 64 channels multi-anode
photomultipliers
– Auto-trigger on 1/3 p.e. at 10 MHz, 12 bit charge output
– SiGe 0.35 µm, 12 mm2, Pd = 350mW
Hold signal
Variable
64 inputs
20-100 ns
Photons
PM
64 channels
Multiplexed Analog
charge output
S&H
Slow Shaper
Variable
Gain
Preamp.
Gain correction
64*6bits
3 discris
thresholds
(3*12 bits)
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S&H
12 bit ADC
Bipolar
Fast Shaper
Multiplexed Digital
charge output
PMF
80 MHz
encoder
Unipolar
Fast Shaper
3 DACs
12 bits
64 Wilkinson
64 trigger outputs
(to FPGA)
LUCID
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Active board pictures
MAROC2 chip bounded at CERN
MAROC side
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64 ch PMT
Lattice side
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MAROC Efficiency curves
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ILC Challenges for electronics
• Requirements for electronics
–
–
–
–
Large dynamic range (15 bits)
Auto-trigger on ½ MIP
On chip zero suppress
Front-end embedded in detector
ASIC
– Ultra-low power : («25µW/ch)
Si wafers
Ultra-low
POWER
W layer
• « Tracker electronics with
is the
calorimetric performance » KEY issue
– 108 channels
– Compactness
• No chip = no detector !!
ILC : 25µW/ch
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FLC_PHY3 18ch 10*10mm 5mW/ch
ATLAS LAr FEB 128ch 400*500mm 1 W/ch
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The front-end ASICs : the ROC chips
SPIROC
Analog HCAL
(SiPM)
36 ch. 32mm²
June 07
• Technological prototypes :
full scale modules (~2m)
• EUDET EU funding (06-09)
• ECAL, AHCAL, DHCAL
• B=5T
HARDROC
Digital HCAL
(RPC, µmegas or GEMs)
64 ch. 16mm²
Sept 06
SKIROC
ECAL
(Si PIN diode)
36 ch. 20mm²
Nov 06
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DHCAL chip : HaRDROC
• Hadronic Rpc Detector Read
Out Chip (Sept 06)
– 64 inputs, preamp + shaper+ 2
discris + memory + Full power
pulsing
– Compatible with 1st and 2nd
generation DAQ : token ring
readout of up to 100 chips
– First test of 2nd generation DAQ
– First test detector integration
• Collaboration with
IPNL/LLR/Madrid/Protvino
– 1m3 scalable detector
– Production of 5000 chips in 2009
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HaRDROC architecture
• Variable gain (6bits)
current preamps
(50ohm input)
• One multiplexed
analog output (12bit)
• Auto-trigger on ½ MIP
• Store all channels and
BCID for every hit.
Depth = 128 bits
• Data format :
128(depth)*[2bit*64ch
+24bit(BCID)+8bit(He
ader)] = 20kbits
• Power dissipation :
1.5 mW/ch (unpulsed)> 15µW with 1% cycle
• Large flexibility via
>500 slow control
settings
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S-curves of 64 channels
50% trigger versus channel number
Dac unit
• 10 bit DAC for threshold
• Noise ~ 1 UDAC (2mV)
• Pedestal dispersion : 0.4
UDAC rms
• Gain dispersion 3% rms
• Crosstalk : < 2%
30 fC
10 fC
Pedestal
Channel number
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SKIROC for W-Si ECAL
• Silicon Kalorimeter Integrated Read Out Chip (Nov 06)
– 36 channels with 15 bits Preamp + bi-gain shaper +
autotrigger + analog memory + Wilkinson ADC
– Digital part outside in a FPGA for lack of time and increased
flexibility
– Technology SiGe 0.35µm AMS. Chip received may 07
1 MIP in SKIROC
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12 bit Wilkinson ADC performance
Skiroc Pedestal Dispersion (Internal ADC)-Gain 1
1085
rms = 0.9UADC
(330µV)
MIP =3 UADC
SKIROC ADC dispersion - channel 18
500
1080
1080
450
1075
400
350
Count (#) - total is 1000
ADC count (#)
1070
1065
1060
300
250
200
150
1055
100
50
1050
1050
1045
0
5
10
15
20
25
channel number (#)
30
35
Pedestal value vs Channel number
40
0
1046
1047
1048
1049
ADC bins (#) mean: 1048.283 std : 0.883
Noise in low gain shaper
SKIROC ADC dispersion - channel 36
100
Skiroc Noise Dispersion (Internal ADC)-Gain 10
5
5
90
4.8
1051
rms = 4UADC
(1.4mV)
MIP=30UADC
80
70
Count (#) - total is 1000
4.6
ADC count RMS (#)
1050
4.4
4.2
60
50
40
30
4
4
20
3.8
10
3.6
0
5
10
15
20
channel number (#)
25
Noise vs Channel number
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30
35
40
0
1055
1060
1065
1070
1075
1080
ADC bins (#) mean: 1071.3 std : 4.629
Noise in high gain shaper
C. de La Taille - microelectronics at OMEGA-LAL
1085
1090
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Front-end board for ECAL
No component
 All features embedded in ASIC
PCB – FRONT
PCB – BACK
An ASU (Active Sensor Unit)
VFE ASIC bonded in a PCB
ASIC buried in the PCB
ASU stitching : zero thickness connection
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Second generation chip for SiPM
• SPIROC : Silicon Photomul.
Integrated Readout Chip
–
–
–
–
–
36 channels
Charge measurement
Time measurement
Autotrigger on MIP or spe
Sparsified readout compatible
with EUDET 2nd generation DAQ
– Chips daisy-chained
– Pulsed power -> 25 µW/ch
• Fabricated in SiGe AMS 0.35 µm
– Submitted in june 07
– Chip area : 30 mm2
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SPIROC main features
• Internal input 8-bit DAC (0-5V) for individual SiPM gain
adjustment
• Energy measurement : 14 bits
– 2 gains (1-10) + 12 bit ADC 1 pe  2000 pe
– Variable shaping time from 50ns to 100ns
– pe/noise ratio : 11
• Auto-trigger on 1/3 pe (50fC)
– pe/noise ratio on trigger channel : 24
– Fast shaper : ~10ns
– Auto-Trigger on ½ pe
• Time measurement :
•
•
•
•
•
•
•
– 12-bit Bunch Crossing ID
– 12 bit TDC step~100 ps
Analog memory for time and charge measurement : depth = 16
Low consumption : ~25µW per channel (in power pulsing mode)
Individually addressable calibration injection capacitance
Embedded bandgap for voltage references
Embedded 10 bit DAC for trigger threshold and gain selection
Multiplexed analog output for physics prototype DAQ
4k internal memory and Daisy chain readout
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SPIROC : One channel schematic
0.1pF-1.5pF
1.5pF
Low gain
Preamplifier
0.1pF-1.5pF
IN
test
15pF
Slow Shaper
Analog memory
50 -100ns
Depth 16
High gain
Preamplifier
Charge
measurement
Depth 16
15ns
Discri
Common to the
36 channels
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ADC
Conversion
Variable delay
80 µs
Trigger
Depth 16
DAC output
12-bit
Wilkinson
READ
HOLD
Fast Shaper
8-bit DAC
0-5V
Gain
Slow Shaper
50-100ns
IN
Gain
selection
Flag
TDC
4-bit threshold
adjustment
10-bit DAC
TDC ramp
Time
measurement
300ns/5 µs
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ValidHoldAnalogb
16
RazRangN
16
Chipsat
16
ReadMesureb
Acquisition
ExtSigmaTM (OR36)
gain
Wilkinson ADC
Discri output
StartAcqt
SlowClock
Hit channel register 16 x 36 x 1 bits
TM (Discri trigger)
Trigger discri Output
36
BCID 16 x 8 bits
Channel 0
gain
36
ValGain (low gain or
high Gain)
Conversion
ADC
EndRamp (Discri ADC
Wilkinson)
Trigger discri Output
StartConvDAQb
TransmitOn
readout
+
36
Wilkinson ADC
Discri output
NoTrig
FlagTDC
RamFull
OutSerie
EndReadOut
Ecriture
RAM
StartReadOut
Rstb
Channel 1
Clk40MHz
..…
…
TDC ramp
ADC ramp
Startrampb
(wilkinson
ramp)
OR36
StartRampTDC
Chip ID register 8 bits
RAM
ChipID
8
ValDimGray
ASIC
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ValDimGray 12 bits
12
C. de La Taille - microelectronics at OMEGA-LAL
DAQ
23
SPIROC performance
• Good analog performance
– Single photo-electron/noise = 8
– Auto-trigger with good uniformity
– Complex chip : many more measurements needed
• bug in the ADC necessitates an iteration
Série1
S-curves
Série2
Série3
Série4
100
Série5
Série6
90
Série7
Série8
Série9
80
Série10
Série11
70
trigger efficiency
Série12
Série13
60
Série14
Série15
50
Série16
Série17
40
Série18
Série19
30
Série20
Série21
20
Série22
Série23
Série24
10
Série25
0
388
Série26
390
392
394
396
398
DAC value
400
402
404
406
408
Série27
Série28
Série29
Série30
Série31
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PMm2 : large photodection area
•
•
•
“PMm2” (2006 – 2009), funded by the
ANR : LAL, IPNO, LAPP and Photonis
Replace large PMTs (20”) by groups of
smaller ones (12”)
– central 16ch ASIC (PaRISROC)
– 12 bit charge + 12 bit time
– water-tight, common High Voltage
– Only one wire out (DATA + VCC)
– Target low cost
– Reuse many parts from MAROC &
SPIROC
Joël PouthasIPN Orsay
Application : large water
Cerenkov neutrino
–
–
–
1ns time resolution
High granularity
scalability
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PArISROC specifications
• Based on a complete 16 channels read out chip
with dedicated for Photomultiplier array
(PARISROC)
• Measurement of Charge and time
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ASIC Architecture
Channel 16
Internal read
Channel 1
Vref
SSH
CRRC2
Slow Shaper
(50 , 100,
200 ns)
Variable Gain
Amplifier
(1-8)
16
charge
inputs
Differential
Fast Shaper
(15ns)
Vref FSH
Vref
SSH
blocks
 slow control signal
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12 bits
ADC
OR
Gain Correction
(8bits)
 new
Track
& hold
Bandgap
variable
delay
Discri
DAC
4 bits
DAC
10 bits
1 digital
charge
output
1 ext.
Common Hold
OR
1 OR
output
16 Trigger
outputs
Threshold
(4bits/ch)
Threshold
C. de La Taille - microelectronics at OMEGA-LAL
24 bits
counter
10MHz
24bits absolute
time
measurement
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3D technology
• Increasing integration
density, mixing technologies
• Wafer thinning to <50 µm
• Minimization of interconnects
• Large industrial demand
©A. Klumpp (IZM)
– Processors, image sensors…
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Major Markets for 3D
[R. Yarema FNAL]
• Pixel arrays for imaging
Pixel arrays with sensors and readout are well
suited to 3D integration since signal processing
can be placed close to the sensor. Current 2D
approaches cannot handle the data rate needed
for high speed imaging.
• Memory
All major memory manufactures are working
on 3D memory stacks. Significant cost
reductions can be expected for large memory
devices. The cost of 3D can be significantly
less than going to a deeper technology node.
• Microprocessors
A major bottleneck is access time between CPU
and the memory. Memory caches are used as
an interface but the area required is significant.
Initial applications for 3D will use Logic to
Memory, and Logic to Logic stacking.
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C. de La Taille - microelectronics at OMEGA-LAL
(Samsung)
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3D consortium
• Collaboration between IN2P3, INFN and FNAL
– SLHC, ILC and SuperB applications
• Chartered 0.13µm and Tezzaron process chosen
–
–
–
–
« IBM compatible » process
Via first : 1-2 µm vias
Assembled by Tezzaron
Run coordinated by FNAL
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Chartered 0.13 um Process
• 8 inch wafers
• Large reticule – 24 mm x 32 mm
• Features
–
–
–
–
–
–
Deep N-well
MiM capacitors – 1 fF/um2
Single poly
8 levels of metal available
Zero Vt (Native NMOS) available
A variety of transistor options with
multiple threshold voltages can be
used simultaneously
•
•
•
•
Eight
inches
Nominal
Low voltage
High performance
Low power
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Tezzaron 3D Process
• Complete back end of line (BEOL) processing by
adding Cu metal layers and top Cu metal (0.8 um)
6 um
Cu
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at OMEGA-LAL
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Tezzaron 3D Process
Example: bonding identical wafers
Cu for wafer bond to 3rd layer
12um
CuCu
bond
Thin second wafer to about
12um to expose super via.
Flip 2nd wafer on top of
first wafer.
Bond second wafer to
first wafer using Cu-Cu
thermo-compression bond.
Orsay, 19 jan 2009
Add metallization to back of
2nd wafer for bump bond or wire
bond.
OR
Add Cu to back of 2nd wafer
to bond 2nd wafer to 3rd wafer
C. de La Taille - microelectronics
at OMEGA-LAL
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Reticule
TX1
TY1
TY 2
A1
B1
B2 A2
TX2
C1
D1 D2
C2
E1
F1
F2
G1
H1 H2 G2
J1
K1 K2
F2
J2
TX1
TY1
TY2
TX2
A1
B1
B2
A2
C1
D1
D2
C2
E1
F1
F2
F2
E2
G1
H1
H2 G2
J1
K1
K2
J2
100 um street
Wafer center line
Alignment area
1 mm
Blowup of wafer center lines
Frame layout
Wafer Map
Orsay, 19 jan 2009
Chip X= 6.4 mm
Yellow = France
Chip Y= 5.5 mm
Green = Italy
Test chip Y=1.9 mm
Blue = USA
Alignment= 1.0x25.9 mm
Magenta = alignment Frame X=26mm, Y=31mm
Grey = test chips
Streets = 100 um
C. de La Taille - microelectronics at OMEGA-LAL
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Three Tier Arrangement for VIP1 Pixel :
FNAL
22 um
Orsay, 19 jan 2009
C. de La Taille - microelectronics
at OMEGA-LALTWEPP-08
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3D for ATLAS
• CPPM :
– move FEI4 from IBM 0.13µm to FEC4 Chartered 0.13µm (2D)
– Target Mosis run 23/1/09
– Fold FEC4 2D chip into FETC4 chip 3D (CPPM, Bonn,LBL) , keep
analog part in analog tier and put a simple register in digital tier
• LAL :
–
–
–
–
Study smaller pixels (50x50µm instead of 50x250)
Match Munich new ATLAS pixel prototype
Target 10 µW/ch => 400 mW/cm2
Design analog tier with low noise low power preamp including
shaping + threshold DAC
– Discriminator in digital tier + dynamic memory
– Study digital coupling to analog tier with discri in digital tier
– Study variants of blocks for FEI4 (preamp, discri,DAC, local
storage…)
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Next steps
• Omega will participate to
march08 run
• Aim at studying 3D design for
low power, small area pixels
• Will submit a chip with
– One analog tier of low power, low
Digital tier
noise preamp, low offset
discriminator for 50x50µ pixels
– One digital tier of local memory,
Analogue
sparsification and readout
Pad
AOP
• Collaboration with
– ATLAS pixel group
– FNAL CMS SLHC (R. Yarema)
– INFN SuperB (V. Re)
Orsay, 19 jan 2009
Pad
Sensor layer
C. de La Taille - microelectronics at OMEGA-LAL
50 mm
37
Conclusion
• MAROC, HaRDROC, SKIROC, SPIROC…
– 4 complex ASICs prototyped in 2007 : 2nd
generation chips
– SoC : System on chip (ADC, TDC, DAQ…)
– Production in 2009 in a dedicated run ILC
main customer
– Many external requests
– Long and difficult measurements…
• Coming up : 3D
– CMOS 130nm
– Basic analog tier for 3D integration in
collaboration with CPPM Marseille aimed at
50x50µm pixels simple readout.
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