Transcript abhay_SLIDESssssssssssssssx

•HISTORY OF PROCESSORS
NOW I AM INTRODUCING THE FIRST
PROCESSOR USED BY THE WORLD WHICH
IS KNOWN AS 8O86 [1978]
Produced
From 1978 to
1990s
Common
manufacturer(s)
Intel
Max CPU clock
5 MHz to 10 MHz
Instruction set
x86-16
Package(s)
40 pin DIP
INTEL 8088 [1979]
Produced
From 1979 to 1990s
Common
manufacturer(s)
Intel
Max CPU clock
5 MHz to 10 MHz
Instruction set
x86-16
40 pin DIP
Package(s)
An Intel 80186 Microprocessor
Produced
From 1982 to present
(the CMOS version)
Common
manufacturer(s)
Intel
Max CPU clock
6 MHz to 12 MHz
Instruction set
x86-16
Package(s)
68-pin
INTEL 80286 [1982]

A 16-bit, 134,000 transistor processor capable of addressing
up to 16 MB of RAM. In addition to the increased physical
memory support, this chip is able to work with virtual
memory, thereby allowing much for expandability. The 286
was the first "real" processor. It introduced the concept of
protected mode. This is the ability to multitask, having
different programs run separately but at the same time. It ran
at 8, 10, and 12.5 MHz, but later editions of the chip ran as
high as 20 MHz. While these chips are considered
paperweights today
An Intel 80286 Microprocessor
Produced
Common
manufacturer(s)
From 1982 to early
1990s
Intel
AMD
Harris Corporation
Siemens AG
 INTEL 386 [1985-1990]
Max CPU clock
6 MHz to 25 MHz

Min feature size
1.5 µm
Instruction set
x86-16 (with MMU)
Package(s)
PLCC 68-pin



The 386 was a 32-bit processor, meaning its data throughput was
immediately twice that of the 286. Containing 275,000 transistors,
the 80386DX processor came in 16, 20, 25, and 33 MHz versions.
The 386 was the first chip to use instruction pipelining, which
allows the processor to start working on the next instruction
before the previous one is complete.
In 1988, Intel released the 386SX, which was basically a low-fat
version of the 386. It used the 16-bit data bus rather than the 32bit, and it was slower, but it thus used less power and thus enabled
Intel to promote the chip into desktops and even portables.
Also, the 386 offered power friendly features such as low voltage
requirements and System Management Mode (SMM) which could
power down various components to save power.
Intel 80386 DX, 33 MHz, foreground
Produced
Intel
AMD
Common manufacturer(s)
IBM
Max CPU clock
12 MHz to 40 MHz
Min feature size
1.5 µm to 1 µm
Instruction set
x86 (IA-32)
Socket(s)
Intel 80386 DX, 33 MHz, foreground
From 1986 to September
2007
132-pin PGA, 132-pin
PQFP; SX variant: 100pin PQFP
INTEL 486 [1989-1994]
The exposed die of an Intel 80486DX2
microprocessor
Produced
From 1989 to 2007
Common manufacturer(s)
Intel
IBM
Max CPU clock
16 MHz to 100 MHz
FSB speeds
16 MHz to 50 MHz
Min feature size
1, 0.8, 0.6 µm
Instruction set
x86
Cores
1
Socket 1
Socket 2
Socket(s)
Socket 3
THE PENTIUM [1993]

The original Pentium performed at 60 MHz and 100 MIPS.

It is also called the "P5" or "P54", the chip contained 3.21 million transistors
and worked on the 32-bit address bus (same as the 486).

It has a 64-bit external data bus which could operate at roughly twice the
speed of the 486.

Pentium is compatible with all of the older operating systems including DOS,
Windows 3.1, Unix, and OS/2. Its superscalar design can execute two
instructions per clock cycle.

The first Pentium chips operated at 5 volts and thus operated rather hotly.
Starting at the 100MHz version, the requirement was reduced to 3.3 volts.
75 MHz classic Pentium processor
Produced
Common manufacturer(s)
Intel
Max CPU clock
60 MHz to 300 MHz
FSB speeds
50 to 66
Min feature size
0.8 µm to 0.25 µm
Instruction set
x86
Microarchitecture
P5
Cores
1
Socket(s)
75 MHz classic Pentium processor
From 1993 to 1999
Core name(s)
Socket 4, Socket 5, Socket 7
P5. P54, P54CS, P55C, Tillamook
THE PENTIUM PRO [1995-99]

INCREASED SPEED IS ACHIEVED BY DIVIDING
PROCESSING INTO MORE STAGES, AND MORE WORK IS
DONE WITHIN EACH CLOCK CYCLE.
. THREE INSTRUCTIONS CAN BE DECODED IN EACH CLOCK
CYCLE, AS OPPOSED TO ONLY TWO FOR THE PENTIUM.
. INSTRUCTION DECODING AND EXECUTION ARE
DECOUPLED, MEANING THAT INSTRUCTIONS CAN STILL BE
EXECUTED IF ONE PIPELINE STOPS (SUCH AS WHEN ONE
INSTRUCTION IS WAITING FOR DATA FROM MEMORY; THE
PENTIUM WOULD STOP ALL PROCESSING AT THIS POINT).
. IT HAS TWO SEPARATE 8K L1 CACHE (ONE FOR DATA
AND ONE FOR INSTRUCTIONS), AND UP TO 1 MB OF
ONBOARD L2 CACHE IN THE SAME PACKAGE.
. THE ONBOARD L2 CACHE INCREASED PERFORMANCE IN
AND OF ITSELF BECAUSE THE CHIP DID NOT HAVE TO
MAKE USE OF AN L2 CACHE ON THE MOTHERBOARD
ITSELF.
. PPRO IS OPTIMIZED FOR 32-BIT CODE, SO IT WILL
RUN 16-BIT CODE NO FASTER THAN A PENTIUM, WHICH
IS A BIG DRAWBACK.
. IT’S STILL A GREAT PROCESSOR FOR SERVERS, BEING
IT CAN BE IN MULTIPROCESSOR SYSTEMS WITH 4
PROCESSORS.
Pentium Pro with 256 KB L2-Cache
Produced
Common
manufacturer(s)
November 1,
1995
Intel
Max CPU clock
150 MHz to
200 MHz
FSB speeds
60 to 66
Min feature size
0.35 µm to
0.50 µm
Instruction se
x86
Microarchitecture
P6
Cores
1
Socket(s)
Socket 8
PENTIUM MMX [1997]





One of the more improved flavors was the Pentium MMX, released in 1997.
The Pentium MMX performed up to 10-20% faster with standard
software, and higher with software optimized for the MMX
instructions.
Many multimedia applications and games that took advantage of
MMX performed better, had higher frame rates, etc.
The dual 8K caches of the Pentium were doubled to 16 KB each. It
also had improved dynamic branch prediction, a pipelined FPU,
and an additional instruction pipe to allow faster instruction
processing.
The line lasted up until recently, and went up to 233 MHz. While
new PCs with this processor are all but non-existent
Pentium MMX 233
MHz (P55C,
80503) top
AMD K6 (1997)
The K6 processor compared, performance-wise, to the new
Intel Pentium II's, but the K6 was still a pentium alternative.
The K6 took on the MMX instruction set developed by Intel,
allowing it to go head to head with Pentium MMX.
. It contained 64KB of L1 cache (32KB for data and 32KB for
instructions).
During its life span, it was released in 166MHz to 300 MHz
versions.
Original K6 (Model 6)
PENTIUM II [1997]

Pentium II is optimized for 32-bit applications. It also
contains the MMX instruction set, which is almost a
standard by this time.

The chip uses the dynamic execution technology of
the Pentium Pro, allowing the processor to predict
coming instructions, accelerating work flow.





Pentium II has 32KB of L1 cache (16KB each for data
and instructions) and has a 512KB of L2 cache on
package.
The chip and L2 cache actually reside on a card
which attaches to the mother.
The L2 cache runs at ½ the speed of the processor,
not at full speed. board via a slot, much like an
expansion card
A Slot 1 Pentium II – front view
Produced
Common
manufacturer(s)
Intel
Max CPU clock
233 MHz to 450 MHz
FSB speeds
66 to 100
Min feature size
0.35 µm to 0.25 µm
Instruction set
x86, MMX
Microarchitecture
P6
Cores
1
Socket(s)
Slot 1
MMC-1
MMC-2
Mini-Cartridge
Others
It ran at a paltry 66 MHz bus speed and ranged from
233MHz to 450MHz.
They used a 0.25 micron design technology for this
one, and allowed a 100MHz system bus.
From mid 1997 to
early 1999
Core name(s)
Klamath
Deschutes
Tonga
Dixon
CELERON [1998]

As a product concept, the Celeron was introduced
in response to Intel's loss of the low-end market

From CELERON Intel removed the L2 cache from
the Pentium II. They also removed the support for
dual processors, an ability that the Pentium II had.

The chip was limited to the 66MHz system bus.

they ditched the plastic cover which the P2 had,
leaving simply the processor on the Slot 1 style
card. This, no doubt, reduced the cost of the
processor quite a bit, but performance suffered
noticeably.



The Celerons with full speed cache operated much
better than the Pentium II's with 512 KB of cache
running at half speed.
Produced
Common
manufacturer(s)
Intel
Max CPU clock
266 MHz to 3.60 GHz
FSB speeds
66 MHz to 800 MT/s
Min feature size
0.25 µm to 0.065 µm
Instruction set
x86, x86-64
Microarchitecture
P6, NetBurst, Core
Socket(s)
Slot 1
Socket 370
Socket 478
LGA775
Socket M
The original Celerons used the patented Slot 1
interface.
Slot 1 Celerons ranged from the original 233MHz up
to 433 MHz, while Celerons 300MHz and up were
available in Socket 370.
From April 1998 to
Present
Core name(s)
Covington
Mendocino
Coppermine-128
Tualatin-256
Willamette-128
PENTIUM III [1999]

The first Pentium III variant was the Katmai (Intel product code 80525). It used a
0.25 µm CMOS semiconductor process. The only differences were the
introduction of SSE and an improved L1 cache controller, which was responsible
for the minor performance improvements over the "Deschutes" Pentium IIs. It
was first released at speeds of 450 and 500 MHz.

It was first released at speeds of 450 and 500 MHz.

Two more versions were released: 550 MHz on May 17, 1999 and 600 MHz
on August 2, 1999. On September 27, 1999 Intel released the 533B and
600B running at 533 & 600 MHz respectively.
A Pentium III Katmai
SECC2 cartridge with
Heatsink Removed

The 'B' suffix indicated that it featured a 133 MHz FSB, instead of the
100 MHz FSB of previous models.

The second version, Coppermine, or 80526, had an integrated full-speed
256 Kib L2 cache with lower latency and a 256-bit bus, named Advanced
Transfer Cache by Intel, which improved performance significantly over
Katmai.

It was built on a 0.18 μm process. Pentium III Coppermines running at 500,
533, 550, 600, 650, 667, 700, and 733 MHz were first released on October
25, 1999. From December 1999 to May 2000, Intel released Pentium IIIs
running at speeds of 750, 800, 850, 866, 900, 933 and 1000 MHz (1 GHz).
Both 100 MHz FSB and 133 MHz FSB models were made.

An additional "B" was later appended to designate 133 MHz FSB models, A Pentium III Coppermine
866Mhz with thermal paste
resulting in an "EB" suffix. 1.13 GHz version was released in mid-2000

It shares with the Coppermine-128 Celeron its 133 MT/s front side bus
left.
AMD ATHLON [1999-PRESENT]

Athlon Classic launched on June 23, 1999. It showed superior
performance compared to the reigning champion, Pentium III, in every
benchmark.

Athlon Classic is a cartridge-based processor.

Athlon Classic used a 512 KB secondary cache. This cache, again like its
competitors, ran at a fraction of the core clock rate and had its own 64bit bus, called a "backside bus" that allowed concurrent system front side
bus and cache accesses.

Initially the L2 cache was set for half of the CPU clock speed, on up to
700 MHz Athlon CPUs. Faster Slot-A processors were forced to
compromise with cache clock speed and ran at 2/5 (up to 850 MHz) or 1/3
(up to 1 GHz).

The second generation Athlon, the Thunderbird, debuted on June 5, 2000.

It was sold at speeds ranging from 600 MHz to 1400 MHz. The major
difference, however, was cache design. Just as Intel had done when they
replaced the old Katmai Pentium III with the much faster Coppermine PIII.

AMD replaced the 512 KB external reduced-speed cache of the Athlon
Classic with 256 KB of on-chip, full-speed exclusive cache.

AMD kept the 64-bit L2 cache data bus from the older Athlons, as a
result, and allowed it to have a relatively high latency.

In October 2000 the Athlon "C" was introduced, raising the mainboard
front side bus speed to 133 MHz (266 MT/s) and providing roughly 10%
extra performance per clock over the "B" model Thunderbird.
Slot-A Athlon
logo on cartridge
Open AthlonThunderbird
slot A cartridge
CELERON II [2000]

Just as the Pentium III was a Pentium II with SSE and a few
added features, the Celeron II is simply a Celeron with a SSE,
SSE2, and a few added features.

The chip is available from 533 MHz to 1.1 GHz.

This chip was basically an enhancement of the original Celeron.

The PSN of the Pentium III had been disabled in the Celeron II.

Celeron II would not be released with true 100 MHz bus support
until the 800MHz edition, which was put out at the beginning
of 2001.
DURON [2000]
In April of 2000, AMD released the Duron "Spitfire".
The original Duron was limited to operating on a 100 MHz
fron-side bus speed (FSB 200).
while the Athlon at the time could run on a bus clock of 133
MHz (FSB 266). Later Durons supported a 133 MHz bus (FSB
266) while Athlon XP ran at 166/200 MHz FSB (FSB 333/400).
In August of 2001, AMD released the Duron "Morgan". This
chip broke out at 950 MHz but quickly moved past 1 GHz.
The morgan core is with 64 KB of L2
AMD Duron "Spitfire" CPU
Produced
From mid 2000 to
2006
Common
manufacturer(s)
AMD
Max CPU clock
600 MHz to 1.8 GHz
FSB speeds
200 MT/s to
266 MT/s
Min feature size
0.18 µm to 0.13 µm
Instruction set
x86
Socket(s)
Core name(s)
Socket A
Spitfire
Morgan
Applebred
PENTIUM IV [2000-CURRENT]
 The Pentium 4 brand refers to Intel's line of single-
core mainstream desktop and laptopcentral
processing units (CPUs) introduced on November 20,
2000
 They had the 7th-generation architecture, called
NetBurst, which was the company's first all-new
Produced
design since 1995, when the Intel P6 architecture of
Common
manufacturer(s)
the Pentium Pro CPUs had been introduced.
 Netburst achieve very high clock speeds (up to 4
GHz).
Intel
Max CPU clock
1.3 GHz to 3.8 GHz
FSB speeds
400 MT/s to 1066 MT/s
Min feature size
0.18 µm to 0.065 µm
 In 2004, the initial 32-bit x86 instruction set of the Instruction set
Pentium 4 microprocessors was extended by the 64-Microarchitecture
bit x86-64 set.
 According to Intel, NetBurst is made up of four newSocket(s)
technologies: Hyper Pipelined Technology, Rapid
Execution Engine, Execution Trace Cache and a
400MHz system bus.
From 2000 to 2008
Core name(s)
x86 (i386, x86-64,
MMX, SSE, SSE2, SSE3
NetBurst
Socket 423
Socket 478
LGA 775
Willamette
Northwood
Prescott
Cedar Mill