Transcript Diapositiva 1

The NA62 front-end chip
Angelo Rivetti-INFN Torino
A. Rivetti
Feb 20th, 2008
From the module to the front-end chip
13.5 mm
12 mm
Pixel matrix
Data and transmission logic
Wire bonding pads
A. Rivetti
Feb 20th, 2008
Specifications
• Pixel size: 300 mm x 300 mm.
• 40 columns with 45 pixels each.
• Chip thickness: 100 mm.
• Chip size: 18-19 mm x 12 mm.
• Power density < 2W/cm2
• Dynamic range: 5000 to 60000 electrons.
Key challenges:
• Time resolution: 200 ps rms.
• Maximum data rate per chip: up to 6Gbit/s.
A. Rivetti
Feb 20th, 2008
Time measurement
• Coarse time measurement by counting clock pulses
• Fine measurement with interpolation -> TDC
Time to digital converters:
Two options possible options:
• Time to amplitude converter.
• DLL based TDC.
A. Rivetti
Feb 20th, 2008
Two possible options:
• Constant fraction discriminator (CFD)
• Time over Threshold correction (ToT)
A. Rivetti
Feb 20th, 2008
Combining options …
CFD + TAC: One TDC per pixel.
• granularity (+)
• efficient use of pixel area (+)
• clock distribution to the pixel (-)
CFD + DLL based TDC.
• No clock to the pixel (+)
• More pixels to be grouped to the same TDC (-)
ToT + DLL based TDC.
• “Digital” correction technique (+)
• More pixels to be grouped to the same TDC (-)
Some R&D needed to select the best one…
A. Rivetti
Feb 20th, 2008
One TDC per pixel: the pixel cell
A. Rivetti
Feb 20th, 2008
One TDC per pixel: chip architecture
A. Rivetti
Feb 20th, 2008
Pixel dead-time vs number of buffers
A. Rivetti
Feb 20th, 2008
ToT approach: the TDC
A. Rivetti
Feb 20th, 2008
ToT approach: chip architecture
A. Rivetti
Feb 20th, 2008
Technology
• CMOS 0.13 mm
• 8 metal level
• analogue components (resistors, capacitors, inductors…)
• Triple well NMOS transistors
• High resistivity substrate
• 1.5 V supply
A. Rivetti
Feb 20th, 2008
First prototypes …
NINO
CFD
80 mm
280 mm
A. Rivetti
Feb 20th, 2008
… and results
C = 200f
200,0p
D
DS (sdev)
DF2 (sdev)
160,0p
Jitter (s)
120,0p
80,0p
40,0p
0,0
0
10000
20000
30000
40000
50000
60000
#electrons
NINO jitter performance in electrical tests
(M. Despeisse et al,)
A. Rivetti
CFD jtter performance
(S. Martoiu et al,)
Feb 20th, 2008
Some remarks
• Results from first building blocks quite encouraging.
• Challenge: preserve the performance at the system level.
• Next steps: more complete prototypes including the digital part
• Two prototypes (one per CFD+DAC, one per NINO+DLL TDC)
• Reduced size prototypes
• For a realistic assessment chips have to be also tested connected to
a pixel sensor.
A. Rivetti
Feb 20th, 2008
For discussion…
• Hypothesis: form factor 5 mm x 2 mm
• Bonding pad pitch: 70 mm.
• Wire bonding pads only on one of the longer side.
Maximum number of pads: 64.
• Number of bonding pads on the short side (22)
would be insufficient.
• The “long column” must be folded. 3x folding with
15 pixel per column can be accomodated.
• An extra small column with 15 pixels would
probably fit as well (or individual building blocks for
testing purposes…)
A. Rivetti
Feb 20th, 2008