Transcript Diapositiva 1

Charge measurement with the TDC per pixel
architecture
A. Rivetti, G. Dellacasa S. Garbolino, F. Marchetto, G. Mazza
I.N.F.N. Sezione di Torino, via P. Giuria 1
Torino, 10125, Italy
A. Rivetti
Gigatracker meeting, dec 2009
Basic facts (1)
Assuming 200 mm thick silicon (1 mip=2.4 fC):
The fraction of particle releasing more than 4 mips is 9 x 10 -3
The fraction of particle releasing more than 5 mips is 6.1 x 10 -3
Key questions:
Where to put the threshold?
How many levels?
A. Rivetti
Gigatracker meeting, dec 2009
Basic facts (2)
 In the TDC per pixel architecture the duration of the CFD pulse is not proportional to the input
charge, so it can not be used to put a threshold on high charges.
CFD pulse duration as a function of the input charge
The information must be extracted at the front-end amplifier
Simplest approach: leading edge comparator after the front-end amplifier
A. Rivetti
Gigatracker meeting, dec 2009
Reminder: front-end amplifier topology
 Transimpedance amplifier with fully differential outputs
 It can handle signals of either polarity. Linear from 5000 to 60000 electrons
 Leakage compensation works for ± 200 nA of leakage current
A. Rivetti
Gigatracker meeting, dec 2009
Front-end amplifier schematics
 Fully differential amplifier with triple well NMOS transistors for maximum insulation
from the substrate
 Class AB output stage to reduce the power consumption
A. Rivetti
Gigatracker meeting, dec 2009
Front-end linearity
 The gain has been set to saturate at 10 fC (maximum expected for “good” signals)
 Hard to set a reliable threshold at 10 fC in this case and practically impossible to
have a higher one
A. Rivetti
Gigatracker meeting, dec 2009
Powering the front-end at 1.4 V
 Linear dynamic range is significantly extended.
 Front-end behavior can be tested in the present chip.
 Bias current is the same, power increases by 15 %.
A. Rivetti
Gigatracker meeting, dec 2009
Reducing the preamplifier gain
 Impact on timing performance must be assessed carefully, but preliminary
simulations show marginal increase (time walk: from 385 to 420 ps peak to peak, jitter
from 66 ps to 75 ps peak-to-peak).
A. Rivetti
Gigatracker meeting, dec 2009
Simple ToT
Preamplifier+leading edge comparator+3 bits counter
 Not enough to get rid of the CFD for timing information, but it provides more level of charge
discrimination.
 Counting on both edges: 3.125 ns time bin. 1 bit = 5.3 fC
A. Rivetti
Gigatracker meeting, dec 2009
Summary
 Only approaches that require minimal hardware modifications have been
considered so far.
 My personal conclusions:
 For a single threshold increase the power supply at the front-end
1. Marginal increase in power
2. No modification to the preamplifier. Timing properties can be assessed
in the present prototype.
 If more than one levels are needed a small counter is preferable.
 Only one comparator
 Same number of bits to be stored
A. Rivetti
Gigatracker meeting, dec 2009