Transcript Session-24 (4/12/05) Part-1 (David Feinstein)

SMU - CSE 8380 Spring 2005
Instructor: Dr. H. El-Rewini
INNOVENTIONS®, Inc
- The survival story of a small
company in the high tech industry
A Guest Lecture
By David Y. Feinstein
April 12, 2005
Dallas, TX
INTRODUCTION
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Why INNOVENTIONS®?
RAMCHECK® and SIMCHECK®- about
Memory and Memory Testing
RotoView® technology for Mobile Computing
and hand-held devices
About patents, inventions, and creativity
Small business survival in the land of giants
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Why
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®
INNOVENTIONS ?
“Innovative products from inventive minds”
Expressive and relatively short name. (The name
INNOVENTIONS was coined by my friend Avery More).
Most important: trademark was available in 1984,
hence the ® mark.
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Abstract Memory Device
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Pack more memory, access data faster, and
retain data at the lowest power.
The memory array(s) take/s the bulk of the “real
estate” of any memory device.
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Memory device types from the
Read/Write family
STATIC RAM
 Asynchronous SRAM
 Synchronous SRAM
 Specialty
Dynamic RAM
 Legacy DRAM - FPM,
EDO, NIBBLE, etc.
 SDRAM
 DDR
 DDR II
 RAMBUS, RLDRAM,
Enhanced DRAM, etc.
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The Memory Zoo: chips
PLCC
DIP, TSOP I, TSOP II
TSOP II
BGA
Historically, memory chips start in DIP package (with 100mils pitch) and migrated to
TSOP (50 mils pitch). In the last five years we have seen the emergence of BGA.
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The Memory Zoo: Modules
Original
SIMM
SDRAM/DDR
DIMM
Memory card
RAMBUS
INNOVENTIONS DDR SODIM
Converter
High
Speed
DDR
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SRAM CELL – a typical 6
CMOS transistors example
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WL – Write Line
BL – Bit lines
Q1 and Q2 constitute a
flip flop.
The flip flop retains
data (as long as Vdd is
applied).
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A DRAM Cell retains data in a
capacitor – which must be refreshed
4-Transistor DRAM cell
6-Transistor DRAM Cell
A single transistor DRAM cell
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Memory array interface to the
outside world
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The row
decoder selects
an entire row
that may have
256 cells.
The column
decoder selects
the actual cell
to be amplified
by the sense
amplifier (a.k.a.
differential read
amplifier).
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DRAM / SRAM COMPARISON
Selection Metrics
DRAM
SRAM
Silicon space per cell
Less (1 transistor per
cell) ->higher density,
lower cost
More (4-6
transistors/cell)->lower
density, higher cost
Power Consumption
More – due to charge
retention/refresh
Less – static operation
Control complexity
More complex due to
refresh, address
multiplexing and more
Less complex
Speed (access time)
Slower -> used in
main memory
Faster –> used in
cache
Reliability
Lower
Higher
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LEGACY DRAM STRUCTURE
Early DRAM used +5V & -12V. In the 80s, Single Vdd = 5V, later reduced to
3.3V.
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Read access for legacy DRAM
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DDR INTERNAL STRUCTURE
DDR uses Vdd=2.5V
DDR II uses Vdd=1.8V.
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Read burst for DDR
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Write burst for DDR
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Introduction to Memory
Testing
Address
Address Decoder
Memory Array
Read/Write Logic
Data
Reduced Functional Model
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Memory Functional Testing
The main faults are as follows:
 Stuck-at Fault (SAF)
 Transition Fault (TF)
 Coupling Fault (CF)
 Neighborhood pattern sensitivity fault (NPSF):
 Active NPSF
 Passive NPSF
 Static NPSF
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Functional Memory Faults
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Traditional functional memory
tests
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Back in the late 60 and early 70s, the small memory
sizes allowed the use of test algorithms like GALPAT
and Walking 1/0 which are O(n2).
Other simpler algorithms with limited detection
capabilities where the Checkerboard, Inverse
checkerboard and Zero One test. All are O(n).
The O(n2) tests have much better coverage than the
simpler O(n) tests. In fact, they had the ability to
locate the error– not just detect it. However, the
increasing size of memory rendered them obsolete
many years ago.
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Modern Memory Tests
(MARCH type)
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MATS, MATS+
Marching 1/0, MATS ++
MARCH X
MARCH C- , and more variants
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Tests for neighborhood pattern
sensitive faults
These tests deal with different geometry of the
neighborhood that can affect each cell. In a
Type-1 neighborhood, we consider the base
cell and the four cells physically adjacent to
the base cell (called the deleted
neighborhood cells). Type-2 neighborhood
consists of (m1+m3+1)* (m2+m4+1) cells in a
rectangle around the base cell.
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The Classic RAMCHECK World’s first portable memory
tester (mid 80s)
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Used 8088 processor.
One 7-Segment LED
display shows ‘E’ for
memory error, ‘6’, ‘4’ for
good 64Kb chip, and
‘2’,’5’,’6’ for good
256Kb.
Later, we added the
1Mbit adapter.
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SIMCHECK (1990)
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SIMCHECK II Line (mid 90s)
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RAMCHECK® base tester (early
2000s)
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RAMCHECK® PLUS (2002)
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RAMCHECK PLUS
“under the hood”
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RAMCHECK® PLUS PRO
(First unit shipped March 31, 2005)
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RAMCHECK stand alone
operation: screen captures
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RAMCHECK PC
Communications software
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RotoView Technology
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Patents and inventions
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A patent gives its owner the right to exclude others
from using the invention for 20 years from the date
of the original application.
Each country has its own patent law. A patent must
be filed locally (or regionally, e.g. European Patent)
in any country where a protection is desired.
The US patent law is based on the “first to invent”.
Only few countries use the notion of “first to file”.
The PCT International treaty allows you to first file in
one country and have a priority date for one year.
An inventor must provide FULL disclosure in the
patent. Therefore, another option is “Trade Secret”.
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About Patents (continue)
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An inventor must be diligent in “reducing the
invention to practice”.
Cost to file and obtain a patent in the USA $5,000$20,000. In Europe, it is more than $25,000.
An invention must be New (rule 35 USC §102). A
combination of ideas must be Unobvious (rule 35
USC §103).
350,000 applications are filed in the US each year.
Currently there are ~6,900,000 patents (most of
them have already expired). Unfortunately, ~90% of
patents are merely “paper patents” (with no major
commercial following).
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Are we able to improve our
creative capabilities?
Yes! The story of my high-school teacher Ms. Marcus.
Example – Strategies by “Interaction Associates”
Associate
Eliminate
Work Forward
Work
Backwards
Assume
Classify
Generalize
Exemplify
Compare
Visualize
Exaggerate
Understate
Predict
Incubate
Purge
Symbolize
Simulate
Search
Combine
Separate
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Creativity with Vacuum Tubes
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Measuring success and
failures
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INNOVENTIONS compared to similar businesses.
The pitfall of going public - OPM.
Accepting and making the most from our failures.
The metrics of success:
Employees and business associates.
Products and technology.
Finance.
A lesson learnt: Time to market => “Time to first
Check”.
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References
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A.J. van Goor, “Testing Semiconductor Memories,
Theory and Practice”, John Wiley & Sons, 1991.
Betty Prince, “High Performance Memories”, John
Wiley & Sons, 2nd Ed. 1999.
Frank S. Tsui, “LSI/VLSI Testability Design”,
McGraw-Hill 1987.
Masakazu Shoji, “High-Speed Digital Circuits”,
Addison Wesley, 1996.
James L. Adams, “Conceptual Blockbusters, A
Guide for Better Ideas”, Addison Wesley, 1986.
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For further information
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“Patent It Yourself” by David Pressman, 10th Edition, Nolo Press
2004 (ISBN: 1-4133-0025-1).
US Patent and Trademark: http://www.uspto.gov
INNOVENTIONS main website: www.innoventions.com
RotoView website:
www.rotoview.com
Memory resources:
www.memoryinformation.com
To contact David : [email protected] or
[email protected]
INNOVENTIONS’ website design credit: Scott LaRoche, Director of
Marketing.
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