Transcript Lecture 2: Combinational Logic

COMP541
Combinational Logic - I
Montek Singh
Jan 14, 2010
1
Today
 Basics of digital logic (review)
 Basic functions
 Boolean algebra
 Gates to implement Boolean functions
2
Binary Logic
 Binary variables
 Can be 0 or 1 (T or F, low or high)
 Variables named with single letters in examples
 Really use words when designing circuits
3
Logic Gates
 Perform logic functions:
 inversion (NOT), AND, OR, NAND, NOR, etc.
 Single-input:
 NOT gate, buffer
 Two-input:
 AND, OR, XOR, NAND, NOR, XNOR
 Multiple-input
Single-Input Logic Gates
BUF
NOT
A
Y
Y
Y=A
Y=A
A
0
1
A
Y
1
0
A
0
1
Y
0
1
Two-Input Logic Gates
OR
AND
A
B
Y
A
B
Y=A+B
Y = AB
A
0
0
1
1
B
0
1
0
1
Y
Y
0
0
0
1
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1
More Two-Input Logic Gates
XOR
A
B
NAND
A
B
Y
Y=A+B
A
0
0
1
1
B
0
1
0
1
NOR
Y
Y = AB
Y
0
1
1
0
A
0
0
1
1
B
0
1
0
1
A
B
XNOR
Y
Y=A+B
Y
1
1
1
0
A
0
0
1
1
B
0
1
0
1
A
B
Y
Y=A+B
Y
1
0
0
0
A
0
0
1
1
B
0
1
0
1
Y
1
0
0
1
Multiple-Input Logic Gates
NOR3
A
B
C
AND4
Y
Y = A+B+C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
1
0
0
0
0
0
0
0
A
B
C
D
Y
Y = ABCD
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
0
0
0
0
0
0
1
NAND is Universal
 Can express any Boolean Function
 Equivalents below
9
Using NAND as Invert-OR
 Also reverse inverter diagram for clarity
10
NOR Also Universal
 Dual of NAND
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Representation: Schematic
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Representation: Boolean Algebra
 More on this next time
F  X  YZ
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Representation: Truth Table
 2n rows: where n # of variables
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Schematic Diagrams
 Can you design a Pentium or a graphics chip that
way?
 Well, yes, but diagrams are overly complex and hard to enter
 These days people represent the same thing with
text (code)
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Hardware Description Languages
 Main ones are Verilog and VHDL
 Others: Abel, SystemC, Handel
 Origins as testing languages
 To generate sets of input values
 Levels of use from very detailed to more abstract
descriptions of hdw
 Think about C++ from assembly level description to very
abstract HLL
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Design w/ HDL
 Two leading HDLs:
 Verilog
 developed in 1984 by Gateway Design Automation
 became an IEEE standard (1364) in 1995
 VHDL
 Developed in 1981 by the Department of Defense
 Became an IEEE standard (1076) in 1987
 Most (all?) commercial designs built using HDLs
 We’ll use Verilog
Uses of HDL
 Simulation
 Defines input values are applied to the circuit
 Outputs checked for correctness
 Millions of dollars saved by debugging in simulation instead of
hardware
 Synthesis
 Transforms HDL code into a netlist describing the hardware
(i.e., a list of gates and the wires connecting them)
IMPORTANT:
 When describing circuits using an HDL, it’s critical to think of
the hardware the code should produce.
Verilog Module
 Code always organized in modules
 Represent a logic “box”
 With inputs and outputs
a
b
c
Verilog
Module
y
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Example
module example(input a, b, c,
output y);
*** HDL CODE HERE ***
endmodule
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Levels of Verilog
Several different levels (or “views”)
 Structural
 Dataflow
 Conditional
 Behavioral
Look at first three today
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Example 1
 Output is 1 when input < 011
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Structural Verilog
 Explicit description of gates and connections
 Textual form of schematic
 Specifying
netlist
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Example 1 in Structural Verilog
module example_1(X,Y,Z,F);
input X;
input Y;
input Z;
output F;
//wire X_n, Y_n, Z_n, f1, f2;
not
g0(X_n, X),
g1(Y_n, Y),
g2(Z_n, Z);
Can also be
input X, Y, Z;
nand
g3(f1, X_n, Y_n),
g4(f2, X_n, Z_n),
g5(F, f1, f2);
endmodule
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Slight Variation – Gates not named
module example_1_c(X,Y,Z,F);
input X;
input Y;
input Z;
output F;
not(X_n, X);
not(Y_n, Y);
not(Z_n, Z);
nand(f1, X_n, Y_n);
nand(f2, X_n, Z_n);
nand(F, f1, f2);
endmodule
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Explanation
 Each of these gates is an
 Like object vs class
instance
 In first example, they had names
not g0(X_n, X),
 In second example, no name
not(X_n, X);
 Later see why naming can be useful
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Gates
 Standard set of gates available
 and, or, not
 nand, nor
 xor, xnor
 buf
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Dataflow Description
module example_1_b(X,Y,Z,F);
input X;
input Y;
input Z;
output F;
 Basically a
logical
expression
assign F = (~X & ~Y) | (~X & ~Z);
endmodule
 No explicit
gates
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Conditional Description
module example_1_c(input [2:0] A,
output F);
Notice
alternate
specification
assign F = (A > 3’b011) ? 0 : 1;
endmodule
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Abstraction
 Using the
digital abstraction we’ve been thinking of
the inputs and outputs as
 True or False
 1 or 0
 What are they really?
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Logic Levels
 Define discrete voltages to represent 1 and 0
 For example, we could define:
 0 to be ground or 0 volts
 1 to be VDD or 5 volts
 What about 4.99 volts? Is that a 0 or a 1?
 What about 3.2 volts?
Logic Levels
 Define a
range of voltages to represent 1 and 0
 Define different ranges for outputs and inputs to
allow for noise in the system
 What is noise?
What is Noise?
 Anything that degrades the signal
 E.g., resistance, power supply noise, coupling to neighboring
wires, etc.
 Example: a gate (driver) could output a 5 volt signal
but, because of resistance in a long wire, the signal
could arrive at the receiver with a degraded value,
for example, 4.5 volts
Noise
Driver
5V
Receiver
4.5 V
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The Static Discipline
 Given logically valid inputs, every circuit element
must produce logically valid outputs
 Discipline ourselves to use limited ranges of voltages
to represent discrete values
Logic Levels
Output Characteristics
VDD
Logic High
Output Range
VO H
Input Characteristics
Logic High
Input Range
NMH
Forbidden
Zone
VO L
Driver
NML
Logic Low
Output Range
GND
Receiver
VIH
VIL
Logic Low
Input Range
Noise Margins
Driver
Receiver
NMH = VOH – VIH
NML = VIL – VOL
Output Characteristics
Logic High
Output Range
VO H
VDD
Input Characteristics
Logic High
Input Range
NMH
Forbidden
Zone
VO L
NML
Logic Low
Output Range
GND
VIH
VIL
Logic Low
Input Range
DC Transfer Characteristics
Ideal Buffer:
V(Y)
Real Buffer:
A
Y
V(Y)
VDD
VOH
VOH VDD
Unity Gain
Points
Slope = 1
VOL
VOL 0
V(A)
VDD / 2
VDD
V(A)
0
VIL VIH
VIL, VIH
NMH = NML = VDD/2
NMH , NML < VDD/2
VDD
VDD Scaling
 Chips in the 1970’s and 1980’s were designed using
VDD = 5 V
 As technology improved, VDD dropped
 Avoid frying tiny transistors
 Save power
 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …
Logic Family Examples
Logic Family
VDD
VIL
VIH
VOL
VOH
TTL
5 (4.75 - 5.25)
0.8
2.0
0.4
2.4
CMOS
5 (4.5 - 6)
1.35
3.15
0.33
3.84
LVTTL
3.3 (3 - 3.6)
0.8
2.0
0.4
2.4
LVCMOS
3.3 (3 - 3.6)
0.9
1.8
0.36
2.7
Reading
 Textbook Ch. 2.1 – 2.6
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