Transcript LUSI-BNL-Detectors-July2007-NvB-v3

Two Dimensional Pixel Detectors
for
LUSI Science
Niels van Bakel
Detectors for LCLS & LUSI Science
XAMPS Detector (BNL)
2D PAD Detector (Cornell)
Detector - DAQ Interface
Schedule, milestones, risks, costs
Summary
LUSI DOE Review July 23, 2007
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Niels van Bakel
[email protected]
Specifications
Intense (1012 ph) and short (100 fs) pulses at 120 Hz
need integrating detectors with fast readout (< 8 ms)
Detector specs, what will be available for LUSI
CXI
XPP
XCS
Readout noise
< 0.3 ph
<1 ph
<<1 ph
Full well capacity
1-103 ph
1-104 ph
1-100 ph
Pixel size
110 μm
90 μm
≤ 35 μm
7602
10242
10242
4-24 keV
4-24 keV
4-24 keV
Number of pixels
Energy range
Quantum efficiency
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> 90% @ 8 keV > 90% @ 8 keV > 90% @ 8 keV
Niels van Bakel
[email protected]
Commercial CCD technology
Active thickness of commercial CCDs (1-50 m) gives poor
quantum efficiency
Pixel sizes < 20 m for standard CCDs
Small area devices or heavy tiling
Charge sharing works against 'photon counting'
Best commercial CCDs have full-well of ~500,000 electrons
One 8 keV photon generates 2200 electron-hole pairs  about 200
photons max full well.
Spec. up to 104
Readout of commercial devices not fast enough
Millisecond readout requires highly parallel readout structure
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Niels van Bakel
[email protected]
Detector Technologies
2D Pixel Array Detector (PAD) - Cornell University
Hybrid pixel detector; ASIC bump bonded to detector diode is
not straightforward
Larger pixels to accommodate bump
Each pixel contains amplifier and digitizer; size constraints
X-ray Active Matrix Pixel Sensor (XAMPS) Brookhaven National Lab
Monolithic devices built on silicon provide simplest structure
Need to develop technology to form transistors directly on
high-resistivity Silicon substrate
No bump-bonding and no on-pixel amplifier allows for smaller
pixel size
LUSI DOE Review July 23, 2007
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Niels van Bakel
[email protected]
XAMPS - BNL
NSLS
Has had a team working to bring advanced detectors to NSLS
users for several years
Primary expertise is embedded computing, system
integration and x-ray science
Relies heavily on Instrumentation Division
Under the leadership of Veljko Radeka it has a long history of
developing detector elements for ionizing radiation
(historically for HEP) and readout electronics
Has good technical resources (total staff ~45) including
semiconductor foundry for detector elements, ASIC design,
detector-readout bonding, custom PCB fabrication, standard
board assembly and testing etc. All of its resources can be
brought to bear on the project.
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Niels van Bakel
[email protected]
BNL Team
Peter Siddons, project leader
Pavel Rehak, Zheng Li, Wei Chen, Rolf Beuttenmuller,
Gabriella Carini, detector elements (Inst. Div.)
Paul O'Connor, Gianluigi De Geronimo, Angelo Dragone,
ASIC design (I. D.)
Kate Feng, Tony Kuczewski, Rich Michta, computer and
user interface (NSLS)
Technical assistance:
John Triolo (I.D.), Denis Poshka (NSLS), PCB assembly,
Don Pinelli (I.D.) wire-bonding
Tony Lenhard, Shu Cheung, Rick Greene, mechanical (NSLS)
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Niels van Bakel
[email protected]
X-ray Active Matrix Pixel Sensor
BNL development proposal:
Switch-matrix structure for XPP experiments
During data accumulation each row of pixels is switched on and the
pixel charge is readout
< 1 photon readout noise
104 photons full-well
ms readout time (< 8 ms)
Extremely challenging spec: >104 S/N, single-shot, fast readout
“Charge-pump” structure for XCS experiments
Charge is stored in a potential well and released in a controlled way
similar to a drift detector
<< 1 photon readout noise, needs different technology
100 photons full-well
ms readout time
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Niels van Bakel
[email protected]
XAMPS Pixel Structure
pn junction reversed
biased
Fully depleted wafer
(400 m) gives good
efficiency
Charge is produced by
photo-ionization
Capacitors and JFET
switches are fabricated
in thin n+ layer
Electrons collect under
pixel (switch is OFF)
Charge is read out by
turning transistor ON,
connecting stored
charge to a buss-bar,
and read out by a
charge-sensitive
amplifier.
LUSI DOE Review July 23, 2007
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Niels van Bakel
[email protected]
Test Structures
32x32 pixels
64x64 pixels
128x128 pixels
256x256 pixels
512x512 pixels
9th
Mask
step
(yellow):
Photo of 4 x 4 array,
Sensor needs about 200 process
deep
p+steps
implant,
features
visible
through
Some new steps for BNL, likeisolation
2nd metallization
layer to keep
from
bulk
different
SiO
2 thickness
the capacitance of the Testing
readout contacts:
lines low Si-Al & Al-Al
Two metal layers are visible
16 Mask steps needed
16x16 pixels, 8x8 pixels, 4x4 pixels, 2x2 pixels, and other test structures are designed.
LUSI DOE Review July 23, 2007
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Niels van Bakel
[email protected]
Risk Mitigation for XAMPS Production
MOU required us to assess project risks:
Largest risk is associated with producing essentially fullwafer devices and the possibility of vanishingly small yield
Attempts to identify an additional foundry led to the IBM
Thomas J. Watson Research Laboratory in Yorktown Heights,
NY, long-time users of NSLS
Discussions with IBM engineers suggested a development
path which promises more than simply risk mitigation
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Niels van Bakel
[email protected]
pMOS Version of XAMPS
JFET versus pMOS:
Both start with high-res.
wafer, but BNL's is
known good, IBM's is
unproven.
Both make implants on
both sides of the wafer
BNL's process needs
careful alignment
between layers
IBM's process is selfaligning for several key
layers
If successful, IBM's
process allows more
complex circuits to be
designed than BNL's
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90m
Polyimid
e
FET gate
FET channel
Capacitor gate
Oxide
Silicon
60m
Niels van Bakel
[email protected]
Alternative Small-pixel Structure
Transistor switch using BNL foundry (4 m design rules)
means that small pixels are difficult.
Transistor switch introduces “kTC noise”
Charge can be stored in a potential well and released in a
controlled way without a switch, similar to controlled drift
detector mechanism.
Single charge transfer step; not a CCD; only one transfer loss
This 'charge pump' technology is ideal for speckle
applications.
Lower noise
Small pixels
Smaller full-well
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Niels van Bakel
[email protected]
Charge Pump Pixel
Charge-pump pixel has
three front-side
implants, uniform deep
n, patterned p+ and n+
p+ rings in n-type
wafer form rectifying
junctions and allow
imposition of electric
fields within bulk
n+ implant at center
forms ohmic contact
for charge extraction
Back-side has uniform
p+ rectifying contact
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Pixel separator
p+
Pump electrodes
p+
Charge
extraction
n+
Niels van Bakel
[email protected]
Charge Pumping
LUSI DOE Review July 23, 2007
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Niels van Bakel
[email protected]
Front-end ASIC
All three technologies present similar properties to
front-end
Different applications have different noise level spec. Driven
by pixel structure more than amplifier
Different applications have different expected signal levels
Charge-sensitive preamp
No problems with detector storage capacitor non-linearity
> 104 dynamic range?
Multiple gains simultaneously
Choose optimal gain for each pixel, on the fly. Effectively
adding ADC bits
New approach with Zero Balance Method
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Niels van Bakel
[email protected]
Zero Balance Method
Divide the dynamic range in
8 intervals
When the Qin > Qp activate
the charge pump
The pump removes a fixed
amount of charge Qp until
the residual in Q f is smaller
than Qp
Count number of removed
quanta (3 bits)
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The residual charge in Cf is
then sampled according to a
CDS scheme
The output is converted with
a 12 bit ADC (total 15 bit)
Niels van Bakel
[email protected]
XAMPS Readout
Row-by-row readout, 1 μs/row
FE-XAMPS ASIC: charge
sensitive preamp, 16x1
multiplexer
8 Fast (>20MHz) 8-channel
ADC's multiplexed e.g. x16
columns = 1024
2 GB/s instantaneous raw data
from ADCs
Data streamed via Front-End
FPGA to LCLS DAQ board
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Niels van Bakel
[email protected]
2D Pixel Array Detector
Collaboration with
the Gruner Group
High resistivity Silicon (500 µm) for direct x-ray conversion.
Reverse biased for full depletion.
Bump-bonding connection to CMOS ASIC.
ASIC limit on size, 21 mm2
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Niels van Bakel
[email protected]
Prototype 3 Layout
~110 microns
Evaluation of prototypes:
Pixel size reduced from 135 μm to 110 μm
Counter redesigned: 12 to 14 bits
Change in gain capacitor => Increase dynamic range
Modified test circuits
LUSI DOE Review July 23, 2007
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Niels van Bakel
[email protected]
Full-lot Prototype
June 2007: Received a 190 x190 pixel
ASIC.
March 2007: Submitted diode sensor.
Bump-bond ASIC to diode sensor:
Single Module Prototype end of 2007
Design full-scale FPGA based readout,
high-speed data transfer
Single module detector housing
LCLS Detector Advisory Committee
reviews (every 6 months).
2D PAD available begin 2009
LUSI DOE Review July 23, 2007
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Niels van Bakel
[email protected]
CXI Data Rates (2D PAD)
Frequency
750 px2
1150 px2
2300 px2
10 Hz
11 MB/s
26 MB/s
106 MB/s
30 Hz
33 MB/s
78 MB/s
317 MB/s
120 Hz
132 MB/s
312 MB/s
1.3 GB/s
Frame
1.1 MB
2.6 MB
11 MB
# Frames
105
110 GB
260 GB
1.1 TB
106
1.1 TB
2.6 TB
11 TB
107
11 TB
26 TB
110 TB
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Data rates
Total data volume
Scalable
16 bit ADC
CXI needs 105 -107
frames: takes 15 min – 24
hours (@ 120 Hz) up to 3
hours - 12 days (@ 10 Hz)
continuous running
Niels van Bakel
[email protected]
FE - DAQ Interface
Detector specific
electrical signals
Registers:
Gain,
integration delay,
integration
window
Controls State Machine
generates low-level detector
specific control signals and
multiplexes raw data from
detector onto links to DAQ
board
Clock 1
LVDS
Analog
Clock 2
to DAQ board
Data
ADC
ADC
DAC register;
bias voltage
Clock 2
Data
Detector
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Configuration State
Machine, e.g. loads DAC
registers to set bias on
detector
FE-board
(FPGA)
LVDS
Timing
Pulse
C
P
U
E
V
R
Niels van Bakel
[email protected]
FE - DAQ Interface
DAQ Board
Event buffer
contains up to 100
- 250 images
(DRAM)
from FE Board
FPGA
Data processing in
PPC with DSP
Run Control
Calibration
data
memory
(DRAM)
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Processed data for storage
Processed data for real-time display
LCLS beam
parameters
C
P
U
E
V
R
Niels van Bakel
[email protected]
Detectors Schedule in Primavera 3.1
Involving 6 Fys.
~3.5 FTE LUSI support
2 new detector elements, 2 or 3 new ASIC designs.
Full resource loaded BNL schedule will be available in XPP & XCS breakout sessions
* Schedule provided and maintained by BNL.
LUSI DOE Review July 23, 2007
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Niels van Bakel
[email protected]
Detectors Milestones
XPP Final Design Review
XPP Design Finalized
XPP Detector Delivered to SLAC
XPP Installation at SLAC Complete
CD-4a
XCS Design Finalized
XCS Detector Delivered to SLAC
XCS Installation at SLAC Complete
Closeout Review
CD-4b
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Jan 03, 08
Mar 24, 08
May 04, 09
Nov 03, 09
Feb 08, 10
Sep 16, 10
Sep 29, 11
Sep 30, 11
Sep 29, 11
Mar 30,12
Niels van Bakel
[email protected]
Detector Cost Estimate
XPP Detector Cost Breakdown ($K)
PED
MS&T
ASSY
Total Cost
$2,199.5
$528.3
$203.1
$2,930.9
XCS Detector Cost Breakdown ($K)
PED
MS&T
ASSY
Total Cost
ASSY
$1,410.9
$399.9
$139.9
$1,950.7
ASSY
MS&T
MS&T
PED
PED
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Niels van Bakel
[email protected]
Summary
BNL builds two distinct detectors for the following programs:
X-ray Pump-Probe
X-ray Correlation Spectroscopy
Very different requirements in terms of full-well and noise
performance.
Two sensor technologies proposed
Started a collaboration with IBM which is very beneficial to the
project and will lead to new and improved device structures
Share with LCLS the Cornell 2D PAD detector
Very challenging data handling requirements can be met
Detector - DAQ interface can scale the DAQ needs of LCLS to
provide high data throughput to storage
LUSI DOE Review July 23, 2007
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Niels van Bakel
[email protected]