Transcript Materials

ISIS1 without p-well
#1
#5
Variable time
Variable time
LED pulse
PG
TG
P1
P2
P3
Capture
Readout
Capture
Readout
● Test setup for charge generation and
4 reset samples
4 signal samples
Next row
selected
capture using red LED light (pulse 1 μs)
● Reset, photogate, transfer gate are
common to all cells
● Four readout columns multiplexed to one
ADC input
● Full correlated double sampling
implemented
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
1
Light Signals from ISIS1 without p-well
Light in 2nd pixel
 First measurements showed spurious
charge and slow charge collection – well
understood now
 The top row and 2 side columns are
unprotected from parasitic charge
collection
Charge in
column 16
 The bottom row is protected by the
output circuitry
 ISIS1 without p-well tested first
 ISIS1 with p-well has very large
transistor thresholds
LED flash in the
3rd time stamp
 Some modifications to the
electronics have been done
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
2
ISIS1 with p-well
Variation of Vt with Vss for ISIS P-Well Test Transistors
14
Measured by Ray Bell
12
Threshold Voltage Vt (for Ids = 1 µA)
10
8
6
Device 4 T7
Device 4 TD1
Device 4 TD2
Device 4 TD5
4
2
0
-2
-4
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
Substrate to Source Voltage Vss
T7: SC poly1
TD1: 1st stage SF (SC)
TD2: Reset (BC) TD5: Row select
ISIS1 with p-well
Expected operation
Vth = 1V (BC)
RG>14V
In practice
RSEL>14V
OD = 13-15V; RSEL = 20 V; RG = 20 V
OD=15V
 If VLR < 0, then VOS = -0.6 V (forward PN
junction)
 The column transistor does not turn on
6V
 The column current loads seem to work:
Column
transistor
+1V
ON
OS
6V
Vth = 8V
10k
Vth = 5V
25 μA
16 columns = 400 μA
VLR <0