Transcript Work Packages 2-5 (Konstantin)

LCFI Detector R&D Status Report
LCFI Detector R&D Status Report
WP2 – Sensor Development
WP3 – Readout and Drive Electronics
WP4 – External Electronics
WP5 – Integration and Testing
 Introduction to the present Detector WP
 Work during the last 6-month period
 Current activities
 Plans
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
1
Introduction to the Detector R&D Work Packages
WP2
Sensor Development
CPCCD and ISIS
WP3
Readout and Drive
Electronics
•Design
•Simulations
•Support
•Design
•Simulations
•Interaction with the
manufacturer
WP4
External Electronics
•Circuit Design
•PCB Design
•Simulations on clock
propagation in CPCCD
•CPCCD transformer
drive
WP5
Integration and Testing
•Bump Bonding (VTT)
•Tests of CPCCD, readout
chips and hybrid
assemblies
•Firmware and software for
tests
•Data analysis
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
2
CPCCD Work
Main detector R&D at LCFI:
Hybrid assembly with Column-Parallel CCD (CPCCD) and CMOS ASIC
 First CPCCD (CPC1) manufactured by e2V:
 20 μm square pixels
 750 (H)  400 (V) pixels
 CMOS readout chip (CPR1) designed at RAL
 Bump-bonded by VTT (Finland)
 CPC1 clocked to 25 MHz stand-alone, metalstrapped gates for efficient clock propagation
 CPC1 optimised for low clock amplitude and
low drive power – works with 1.9 Vpp clocks
 Readout chip has amplifiers, 5-bit ADCs and
FIFO per column
Bump-bonded CPC1/CPR1 in a test PCB
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
3
CPCCD Work
5.9 keV X-ray hits, 1 MHz column-parallel readout
Voltage outputs, noninverting (negative
signals)
Charge outputs,
inverting (positive
signals)
Noise 60 e-
Noise 100 e-
 First time e2V CCDs have been bump-bonded
 High quality bumps, but assembly yield only 30% - reason still
unclear
 Differential non-linearity in ADCs (100 mV full scale) – addressed
in CPR2
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
Bump bonds on CPC1
under microscope
4
CPCCD Work – Hybrid Assembly Testing (WP5)
Yield summary from batch 1
Assembly
Left hand side chip
Right hand side chip
CCD
1
OK
OK
OK
2
OK
OK
Problem
3
OK
OK
Problem
4
OK
Low resistance CGND-VDD
Problem
5
OK
OK
OK
6
OK
Short CGND-VDD
OK
7
Subtle defect (VPRE-VDC)
Short CGND-VDD
OK
Summary:
● Only 4 complete assemblies fully working, out of 13 (30% yield)
● Right hand side chips show problems:
● Short between the power supplies or defective in other ways
● Parasitic connection to SS
● Readout chips diced by IBM exhibit yield close to 100%
● All CCDs have been DC probed at e2V – 23 good chips (out of 24).
● Dicing has been checked, does not seem to be the problem
● What is the explanation?
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
5
CPCCD Work – Hybrid Assembly Testing (WP5)
Possible problem explanation (1)
CGND pad, parasitic connection to SS?
Mechanical damage?
Right hand side of the CPCCD
SS
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
6
CPCCD Work – Hybrid Assembly Testing (WP5)
Possible problem explanation (2)
Right hand side of the CPCCD
CGND pad, parasitic connection to SS?
Mechanical damage?
CGND
SS
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
7
CPCCD Work – Hybrid Assembly Testing (WP5)
Right-hand side CPR1, 100 mA between CGND and SS (360 Ω between them)
Thermal images
Batch 1, Assembly 2, right hand side chip
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
8
CPC2 Design
No
connections
this side
Clock bus
 Three different chip sizes with
common design:
 CPC2-70 : 92 mm  15 mm
image area
Charge
injection
 CPC2-40 : 53 mm long
Extra pads for clock
monitoring and
drive every 6.5 mm
Image area
Standard
Field-enhanced
Standard
Temperature
diode on
CCD
Main clock
wire bonds
CPR1
CPR2
 CPC2-10 : 13 mm long
 Compatible with CPR1 and
CPR2
Four 2-stage SF in
adjacent columns
 Two charge transport sections
Four 1-stage and 2stage SF in adjacent
columns
Main clock
wire bonds
 Choice of epitaxial layers for
different depletion depth: 100
.cm (25 μm thick) and 1 k.cm
(50 μm thick)
 Baseline design allows few MHz
operation for the largest size
CPC2
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
9
CPC2 Clock Driving
 CPC1 did not have optimal drive conditions due to single level metal
 Novel idea from LCFI for high-speed clock propagation: “busline-free” CCD:
 The whole image area serves as a distributed busline
 50 MHz achievable with suitable driver in CPC2-10 and CPC2-40 (L1
device)
 Transformer drive for CPC2, will evolve into dedicated driver chip
1 mm
Φ1 Φ2
Φ2 Φ1
To multiple
wire bonds
Level 1 metal
Polyimide
Level 2 metal
To multiple
wire bonds
Φ1 Φ2
Φ2 Φ1
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
10
CPC2 + ISIS1 Wafer
2 ISIS chips
CPC2-40
CPC2-70
CPC2-10
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
11
CPC2 + ISIS1 Manufacture
● Delivery was scheduled to March 2005
● Delays at e2V due to equipment breakdown
● Operator error caused the entire batch to be scrapped
● e2V immediately started new batch at their expense
● First devices expected mid July
● “Bad batch” processed to 1st polysilicon, could be used for
thinning studies
● New diamond grinder at e2V comes next month
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
12
In-situ Storage Image Sensor (ISIS)
 Beam-related RF pickup is a concern for all sensors converting charge into
voltage during the bunch train;
 The In-situ Storage Image Sensor (ISIS) eliminates this source of EMI:
 Charge collected under a photogate;
 Charge is transferred to 20-pixel storage CCD in situ, 20 times during the 1
ms-long train;
 Conversion to voltage and readout in the 200 ms-long quiet period after the
train, RF pickup is avoided;
 1 MHz column-parallel readout is sufficient;
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
13
In-situ Storage Image Sensor (ISIS)
 Additional ISIS advantages:
 ~100 times more radiation hard than
CCDs – less charge transfers
 Easier to drive because of the low clock
frequency
 ISIS combines CCDs, active pixel transistors
and edge electronics in one device: specialised
process
 Development and design of ISIS is more
ambitious goal than CPCCD
Plus additional logic for row selection
and clock gating (not shown)
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
14
ISIS1
 “Proof of principle” device (ISIS1) designed by e2V:
 1616 array of ISIS cells with 5-pixel buried channel
CCD storage register each;
 Cell pitch 40 μm  160 μm, no edge logic (CCD
process)
 Size  6.5 mm  6.5 mm
● Test board designed by a
Sandwich student at RAL
● ISIS1 fits into 100-pin socket
● Software being written
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
15
Simulations on CMOS-based ISIS
● Targeting 0.25 μm or 0.18 μm process
● 3.3 V maximum voltage
● 6.5 nm SiO2 as both CCD and transistor
gate dielectric
● Non-overlapping polySi gates (0.35 μm
gap, 0.25 μm design rules )
Simulations for the next generation
CMOS-based ISIS2
● Thin oxide unfavourable for the CCD
structure – dual gate oxide possible
● LCFI solution – modify the buried channel
implant, keep one oxide only
● Major simplification, reduce costs
Keeping in touch with:
● Jim Janesick (Sarnoff) – simulations,
advice, possibly MPW
● Chronicle Technology – design
● e2V: David Burt, Ray Bell – CCD experts
● “Fine Pixel ISIS” – new concept from
e2V
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
16
Analytical and simulated doping profiles
DIOS simulated doping (part of ISE-TCAD)
● P+ shield implant: 800 keV (B), 51011 cm-2
Analytical profiles:
● Buried channel: 200 keV (P), 41011 cm-2 and
40 keV (P), 31011 cm-2
Gaussians
● Annealed at 1050 C for 40 min
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
17
Alternative ISIS structure
Proposed super-pixel
Apertures
in p-well
4µm, 4Ø line
Charge can be collected
when a high phase is over
a p-well aperture
20 µm
•Pure CCD process, simpler
than the ISIS
but
•Too many transfers?
•Radiation damage concerns
20 µm
•Complicated output structure
Commercial in confidence
WP3 : CPCCD Readout Chip CPR2
Bump bond pads
Voltage and charge amplifiers
125 channels each
Analogue test I/O
Digital test I/O
5-bit flash ADCs on 20 μm pitch
CPR1
Cluster finding logic (22
kernel)
CPR2
Sparse readout circuitry
FIFO
 CPR2 designed for CPC2
 Results from CPR1 taken into account
 Designed by the Microelectronics Group at RAL
 Size : 6 mm  9.5 mm
Wire/Bump bond
pads
 0.25 μm CMOS process (IBM)
 Manufactured and delivered February 2005
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
19
WP3 : CPR2
● Improved clock distribution, should improve ADC performance
● Sparse readout circuitry with position and timestamp, outputs 49 pixels/cluster
● Charge amplifiers:
 Half with 3 fF feedback capacitor (as in CPR1)
 Half with 2 fF capacitor for increased gain
● Voltage amplifiers:
 Selectable 10 ns low-pass filter (was 5 ns in CPR1)
● Direct analogue outputs from one voltage and charge amplifier
● Three analogue inputs to one voltage channel triplet
● Test register with 3 functions:
 Input to sparsifying logic
 ADC data capture
 Selection of an ADC channel for direct output
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
20
WP3 : Testing CPR2
● Test board made at Oxford U
● Work in the CCD lab has begun
● First results indicate the chip is operational
● Testing at RAL/ID imminent
● 2 wafers for bump-bonding available
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
21
WP4 : Transformer drive for CPC2
 Tests of planar transformers with
dummy capacitive load
 Different planar transformers on 10layer PCB
 Requirements: 2 Vpp at 50 MHz over
40 nF (half CPC2-40)
 Size : 1 cm
 Frequency scan with network
analyser, performance promising
 Parasitic inductance of bond wires is
a major effect – fully simulated
 Air core operation from 1 MHz to
> 70 MHz unloaded
 Prototypes ready to be incorporated
into the CPC2 test board (under design
now at Oxford U)
IC driver could be a better solution
Design of CPCCD driver chip - CPD1 in WP3
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
22
WP4 : External electronics
Base VME module (BVM2):
● Large FPGA on-board
● 32 TTL I/O
● 32 LVDS I/O
● Two 1M16-bit SRAM
● Two external clocks
● Daughterboard for extensions: delay
lines, clock management, etc.
● Workhorse for the next 3 years
● Two modules manufactured (ver. 1)
● Second version being designed
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
23
Immediate Plans
WP2:
● Get CPC2 and ISIS1
● Continue ISIS simulations,
WP3:
● Provide support for CPR2 tests
● Start the design of CPD1
WP4:
● Design motherboards for CPC2+CPR2 (bump-bonded and stand-alone)
● Transformer drive, work on the driver chip
WP5:
● Test CPR2, CPC2, ISIS1
● Bump-bond CPC2 to CPR2 and test
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
24
CPCCD Work – Hybrid Assembly Testing (WP5)
Readout Chip Dicing – Upper Left Corner
IBM dicing
VTT batch 1
VTT batch 2
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
25
How CPC1+CPR1 work
OG RG
RD
OD
X-ray signal ≈ 200 mV
+15.2 V
+18.0 V
≈ +14.0 V
BC
2.5 V
SC
BLR
110 µA
+
LPF
ADC
Correlated Double
Sampling
Gain ≈ 40
FB_V
OG
+2.0 V
CPC-1
RD
FB_Q
CPR-1
VDC
3 fF
+17.0 V
BC
_
≈ +14.0 V
ADC
+12.7 V
X-ray signal ≈ 90 mV
Floating CPR-1 ground
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
26
Reset transistor
Source follower
Row select
transistor
reset gate
transfer
Design A
photogate
gate
storage
pixel #1
storage output
pixel #20
gate
VDD
row select
sense node (n+)
To column load
n+
buried channel (n)
p+ well
p+ shielding implant
reflected charge
Charge collection
reflected charge
High resistivity epitaxial layer (p)
substrate (p+)
reset gate
transfer
Design B
photogate
gate
storage
pixel #1
storage
pixel #20
output
gate
VDD
row select
sense node (n+)
n+
buried channel (n)
p+ well
reflected charge
Charge collection
reflected charge
High resistivity epitaxial layer (p)
substrate (p+)
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
27
4
5
Storage gate 3
6
Storage gate 2
RSEL OD
RD
RG
1
7
8
OS
to column load
Output node
Output gate
Photogate
Transfer gate 8
20
19
Charge
Storage
generation
Transfer
18
17
Readback from gate 6
Idea by D. Burt and R. Bell (e2V)
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
28
Cluster Finding in CPR2
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
5
0
0
0
0
0
5
5
0
0
0
0 0
0
5
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
Cluster found
Expanded cluster to be read out
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
29
CPCCD Work – Hybrid Assembly Testing (WP5)
Yield summary from batch 1
Assembly
Left hand side chip
Right hand side chip
CCD
1
OK
OK
OK
2
OK
OK
Problem
3
OK
OK
Problem
4
OK
Low resistance CGND-VDD
Problem
5
OK
OK
OK
6
OK
Short CGND-VDD
OK
7
Subtle defect (VPRE-VDC)
Short CGND-VDD
OK
Problem description:
● Parasitic ohmic connection between right hand side chip substrate (CGND) and
CCD substrate (SS)
● Should see reverse-biased diode between CGND and SS
● The problem disappears when right hand side chip is removed
● Not caused by contamination, resistance too small (e.g. 360 Ω)
Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory
30