Transcript Fabrication

Basic CMOS
CMOS is multiple layers of conducting material, separated by insultion.
Insulation
Metal 2
Metal 1
Polysilicon
Diffusion
Substrate
Contacts/vias are cuts in the insulation to connect layers
The interaction of Polysilicon & Diffusion creates transistors
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Wafer Processing
Czochralski process
direction of pull and rotation
crystal holder
Melt silicon at 1425 degrees C
Add impurities to dope crystal
seed
growing crystal (ingot)
Spin and gradually extract seed crystal
Slice into wafers, 0.25mm to 1.0mm
molten silicon
Polish one side, sand-blast the other
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Basic Patterning
Add material (e.g., silicon dioxide (SiO2))
photoresist
Apply photoresist
silicon wafer
Expose through a mask
Develop and etch resist
SiO2
UV light
mask
Etch material
Remove resist
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Adding Material: Growing SiO2
Expose wafer to oxidizing atmosphere at high temperature
Wet process: atomosphere with H20 @ 900-1000 degrees C
Dry process: pure O2 @ 1200 degrees C
Oxide grows both ways
SiO2 has roughly twice the volume of Si
Half above, Half below
SiO2
substrate
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Adding Material: Other Techniques
Diffusion and Ion Implantation
Adds dopants to silicon
CVD: Chemical Vapor Deposition
Silicon, silicon oxide, silicon nitride, etc.
Sputtering and thin-film deposition
Aluminum and polysilicon
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Photoresist
UV light sensitive organic material
Two types of resist
Positive resist: UV light breaks it down
Negative resist: UV light hardens it
Selectively expose through a mask
Masks are glass plates
patterned areas stop UV light
Develop (harden) desired areas by heating
Remove unwanted resist
Use weak organic solvent
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Etch Material
Etch using selective solvent
Buffered HF dissolves SiO2 but not Si
Photoresist protects areas from etching
Plasmas, sputtering, etc.
Excited ions blast away material
Remove resist with strong organic solvent
silicon wafer
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Mask Making
Traditionally a lithographic process
Rectangles are 'flashed' onto photographic plate
Mechanical alignment limits precision
Electron beam techniques are now widely used
Write each pixel sequentially
Both techniques generate a reticle
Typically 10X larger than final size
10X reticle is used to produce final mask
Step-and repeat process
10X reticle
Mask
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Wells
Transistors formed on opposite substrate
Source Gate Drain
n-type transistors formed on p-substrate
p+
p+
p-type transistors formed on n-substrate
n-SUBSTRATE
Substrate (wafer) doped p-type or n-type
Opposite type wells for other transistors
p-substrate implies n-wells
n-substrate implies p-wells
Source Gate Drain
n+
p-WELL
n+
Ohmic contacts to bias wells and substrate
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Example p-well CMOS Process
Make p-wells
Lay down polysilicon for gates
Diffuse source and drain regions
Lay down metal for interconnect
Cover it all with glass
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Making p-wells
Start with a wafer doped with n-dopant (e.g., arsenic)
Grow field oxide (Si02)
Add resist, mask and expose, develop and remove resist
Use p-well mask
Etch SiO2 using HF
b
b
Diffuse p-type dopant (e.g., boron) b
b
b
boron ions
b
b
b
b
b
n-SUBSTRATE
b
b
b
b
p-WELL
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Grow Gate Oxide (thinox)
Use thinox mask to etch active regions
regions for n-type devices
p-wells already exposed
p-WELL
n-SUBSTRATE
Grow thin oxide layer
Carefully controlled: typically 500 angstroms
p-WELL
n-SUBSTRATE
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Add polysilicon
Cover entire die with polysilicon
Etch with poly mask
For gates and wires
Undoped polysilicon has very high resistance
Must be doped to be a good wire
p-WELL
n-SUBSTRATE
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Make source and drain regions
Self-aligned silicon gate process
Polysilicon gate serves as mask for source and drain
Minimizes overlap, maximizes performance
Dope polysilicon in same step
Use p+ mask and complement
Entire wafer is doped either p+ or n+
Makes sure all polysilicon is doped
Make ohmic contacts
To substrate and wells
p+
p+
n+
n+
p-WELL
n-SUBSTRATE
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Metalization
Cover wafer with SiO2
Etch oxide for contacts
Either poly or diffusion
Sputter on aluminium
Etch aluminium leaving wires
p+
n-SUBSTRATE
p+
n+
n+
p-WELL
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Passivation
Cover wafer with overglass
Prevents shorts due to dust, etc.
Makes finished wafer easier to handle
Etch overglass for bonding pads
Contact cuts
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Complete Fabrication
(a) field oxide etching
n-SUBSTRATE
(b) p-well diffusion
p-WELL
n-SUBSTRATE
(c) field oxide etching
p-WELL
n-SUBSTRATE
(d) gate oxidation
p-WELL
n-SUBSTRATE
(e) polysilicon definition
p-WELL
n-SUBSTRATE
(f) p-plus diffusion
p+
p+
p-WELL
n-SUBSTRATE
(g) n-plus diffusion
p+
p+
n+
n+
p-WELL
n-SUBSTRATE
(h) oxide growth
p+
p+
n+
n-SUBSTRATE
(i) contact cuts
p+
n-SUBSTRATE
p+
n+
n+
p-WELL
n+
p-WELL
(j) metalization
p+
n-SUBSTRATE
p+
n+
n+
p-WELL
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Imperfect Fabrication Process
Mask making dust, focusing
Growing oxide – warping in furnace, uneven reactions
Resist – over exposed, not hardened enough
Etching – overetch of resist and/or oxide
Multiple layers – mask alignment (self-aligning gates helped a lot)
Packaging – bonding wires to pins of package, handling
(macro rules)
These problems lead to rules governing layout
Rules can be very specific often resulting in 100 page documents
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Minimum Width Rules
In wires
step coverage on
steep oxide cliffs
In transistors
safeguard against
radically affecting
circuit performance
In contacts/vias
must be wide enough
for etchant to actually
reach layers to be
contacted – contacts are
larger for higher-up layers
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Minimum Separation Rules
In wires
far enough apart to
prevent short circuits
In transistors
separate n-type and p-type diffusion
regions enough to ensure wells are
properly formed
In contacts/vias
put vias between different layers
far enough apart to prevent
very irregular terrain from forming
it may not be possible to stack vias
and ensure that there is no short
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Overlap and Overhang
In transistors
ensure transistor will
be off by adequate
overhang of gate
In contacts/vias
may be wider than wires to ensure
there will be sufficient contact
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Geometric Rules from Electrical Considerations
Substrate/well contacts near transistors
Must make sure fourth transistor terminal is properly connected
Keeping connections close minimizes latch-up problems
Input protection (against current spikes)
Construct high-resistance on input pads to slow down current surges
Metal migration in power/ground lines
Movement of metal atoms in direction of current flow eventually
causes the wire to break
Larger than minimum size is needed depending on number of devices
connected to a specific wire
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Types of Rules
Absolute micron rules
Most precise, most complex
Mead and Conway Lambda () rules
All rules in terms of 
Simplest (and least precise) rules
Used in Mentor Graphics editor
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Lambda Rules
Relative rather than absolute
Scalable rules with technology advances
Definition:
off by < 1  –> no problem
off by > 2  –> failure possible
off by < 2  and > 1  –> performance loss only
One page of rules rather than 100 (give up some possible optimizations)
Examples
2
1
2
diff
poly
at 1 misreg. poly over diff (xtor)
at 2 may break diff wire
2
any closer and poly gate
may be shorted to GND
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SCMOS Rules
Polysilicon rules
polysilicon
2
minimum width: 2
3
minimum poly-poly spacing: 3
minimum poly-diffusion spacing: 2
2
Diffusion rules
6
minimum width: 6
minimum diff-diff spacing: 4
diffusion
4
minimum ndiff-pdiff spacing: 13
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More Design Rules
Transistor rules
minimum transistor width: 6
6
minimum poly overhang: 2
diffusion
4
minimum diff overhang: 4
polysilicon
2
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Metal Rules
First-level metal
metal1
minimum width: 3
3
minimum spacing: 3
6
7
metal1 size for contact: 6
3
metal1 size for via: 7 
Second-level metal
4
minimum width 4
metal2
minimum spacing 3
3
4
metal2 size for via: 7
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