Transcript Document
Lucas-Lehmer Primality Tester Presentation 5 February 22, 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Overall Objective: Modular Arithmetic unit with a creative use Design Manager: Prateek Goenka This is my presentation, there are others like it but this one is mine Status • Finished – – – – – – Project Chosen C simulations Behavioral Verilog Structural Verilog Revised Floor Plan Schematics ( 95%) • In Progress – Simulation of Schematics • To Do – Simulations – Layout Highlights of the Week • Working on top level schematics and simulations, top-level is currently blocked by a single module. • Minor verilog revisions and testing, not yet incorporated into schematics. Mostly removing logic. • Power testing of modules that are available, considering alternatives. Design Decisions • Current Implementation: – Power usage a little high – Log shifters have to go, expensive – Many easy optimizations to do before moving on • Future: – – – – Possible Alternative adders and shifters. Final constraints for p need to be set Expose mod unit for alternative uses No extra functionality, but exposing mod unit beyond “built-in” application would be good. Log Shifter Issues • Overkill, expensive, not necessary, pointless for our design goals. • Large area, many transistors, very power hungry. Good for speed, but not for us. • A single instance in our tests consumed 140.4uW, many instances needed, good place to start worrying about power. • One of the few modules we can be flexible with. Shifter Schematic Simulation of Mod Add x=68, y=128 P=7, mod by 127 x+y = 196 196 mod 127 = 69 Schematic for Mod Add What we have completed Module schematic simulation Registers yes Yes mod calc yes Yes counter yes Yes compare yes Yes check zero yes Yes fsm no No top level no No partial product yes No mod add yes Yes sub 2 yes yes Transistor Counts and Power Module Transistor Count / Power FSM 300 Mod Calc 2440 Counter 1656 / 53.81uW Mod Multiply mod add unit shifters 15302 / ? 128.8uW 140.4uW each Registers 1848 Compare for zero Total 92 21638 Block Area Estimates Module Area (μm2) FSM 900 Mod Calc 3500 Counter 6000 Mod Multiply 75000 Registers 3000 Compare for zero 300 Total 88300 Floorplan What’s Next • Alternate uses for mod unit • Improve verilog, add to schematic • Optimize, optimize – New adders, shifters, logic reduction, lowpower • Power testing of possible alternative components • Finish the schematic • Do the layout Questions?