Transcript mem

Memory Vocabulary
• ROM – Read Only Memory - a type of memory
that cannot be written, can only be read. Contents
determined a manufacture time.
– ROM is non-volatile – contents remain even when
power is off.
• PROM – Programmable ROM – a type of memory
whose contents can be programmed by the user
– OTP – One Time Programmable, a PROM is OTP if
contents can be programmed only once.
• EEPROM – Electrically Erasable PROM –
contents be erased electrically by the user.
– Memory is not alterable under ‘normal’ operation.
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Memory Vocabulary
• RAM – Random Access Memory – memory that
can be both read and written during normal
operation.
– Contents are non-volatile, will be lost on power off.
• SRAM – static RAM – has the following
characteristics:
– Read, Write operations take equal amounts of time
– Access to any ‘random’ location takes same amount of
time.
– Fastest access time of memory types.
– Basic memory cell is a latch, takes 6 transistors per
memory bit.
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Static Random Access Memory (SRAM)
• The serial EEPROM had low pin count because of serial
I2C interface
– Speed was sacrificed
– Random access read took 5 bytes (3 bytes to set address, 2 bytes
for read). Total of 45 bit times (5 * 9), @400 KHz this took 2.5 s
* 45 = 112.5 s!
– Write speed was slow because non-volatile memory (page write
took about 6.5 ms for 64 bytes, or about 101  s/byte.
• An SRAM (Static Random Access Memory) has:
–
–
–
–
equal read/write times, measured in nanoseconds
volatile (contents not maintained when power removed)
equal cycle time, access time
typically has a parallel interface
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Typical SRAM Control Lines
KxN
Address[log2(K)-1:0]
CS
OE
W
M
E
M
Data[N-1:0]
Data bus is
bidirectional
Chip Select – must be asserted before Memory will respond
to read or write operation. If negated, data bus is high
impedance.
OE – Asserted for read operation, Memory will drive data
lines.
W – Asserted for a write operation (Memory inputs data from
data pins, processor writes to memory).
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Bit Line Bias
Row Decode
Row
Address
Internal
Architecture
Cell
Memory
Organization
Word lines
(1 per row)
Column
Address
Sense Amps
Column Decode
Data lines
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Bit lines
(2 per column)
5
Static Ram Cell
Wordline
B (bitline)
BB (bitline_bar)
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Cypress 8K x 8 SRAM
Multiple Chip Enables – more
flexibility
Data bus is bi-directional (8 I/O
lines).
Note: a more precise name for
this memory is Asynchronous
SRAM.
It has no clock input, any change
on address inputs accesses a new
location.
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Read Cycle
Cycle Time – how fast can I start another operation?
Access Time – how fast is data ready?
For SRAMs, Cycle Time = Access Time, this is a feature of
SRAMs.
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Write Cycle
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Write Timings
Notice that
Write Cycle =
Read Cycle.
All volatile
RAM types
have this
feature.
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PIC To SRAM
PIC
‘#’ means low
true
8Kx8
RA[7:0]
RB[4:0]
RC[7:0]
Vdd
RD0
RD1
A[7:0]
A[12:8]
IO[7:0]
CE2
OE# CE1#
WE#
To read: Address on RA, RB. RC port is all inputs; RD0 = ‘0’,
RD1 = ‘1’.
To write: Address on RA, RB. RC port is all outputs; RD0 = ‘1’,
RD1 = 0.
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Expanding Memory
RAM1
8Kx8
A[7:0]
A[12:8]
IO[7:0]
CE2
OE# CE1#
WE#
RA[7:0]
RB[4:0]
RC[7:0]
RB5
RD0
PIC
RD1
RAM0
8Kx8
A[7:0]
A[12:8]
IO[7:0]
CE1#
CE2
OE#
WE#
RAM1 accessed
when RB5 = 1
RAM0 accessed
when RB5 = 0
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More Memory
RB[4:0], RA[7:0]
RC[7:0]
RD0
RD1
PIC
13
8
RAM0
A[12:0]
IO[7:0]
OE#
WE#
CE1#
RAM1
A[12:0]
IO[7:0]
OE#
WE#
CE1#
RB[6:5]
2-to-4 decoder
RB[6:5]=00
2
0
RB[6:5]=01
1
RB[6:5]=10
2
RB[6:5]=11
3
chip select decoding
RAM2
A[12:0]
IO[7:0]
OE#
WE#
CE1#
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RAM3
A[12:0]
IO[7:0]
OE#
WE#
CE1#
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Memory Map
Total memory = 4 * 8K = 32 K ( 25 * 210), 15 address lines
Selects chip
RB[6:5]
Selects location within chip
RB[4:0],RA[7:0]
1 1
4 3
1 1 1 0 0 0 0 0 0 0 0 0 0
2 1 0 9 8 7 6 5 4 3 2 1 0
0 0
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1
0x0000 low RAM0
0x1FFF high
0
0
1
1
0
1
0
1
0x2000
0x3FFF
0x4000
0x5FFF
1
1
0
0
1 1
1 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1
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low RAM1
high
low RAM2
high
0x6000 low RAM3
0x7FFF high
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Other SRAM Types
• SSRAM - Synchronous SRAM
– Has a clock input
– Address, data lines latched on clock edge
– Can perform burst cycles
• What is a burst cycle?
– After first data value is output based upon address, data
values in successive locations are output without
needing to change address bus
– Internal counter used for address value
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Synchronous SRAM (SSRAM)
Note clock lines to SRAM. A DDR (Double Data Rate)
SSRAM means that data is clocked on both clock edges.
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SSRAM Normal Cycle vs Burst Cycle
Address ready,
Data ready in
clocks.
Address ready, 1st data ready in 2 clocks, successive
locations ready in successive clocks. This burst
cycle is a 2-1-1-1 cycle. Diagram shows burst
suspended for 1 clock between 3rd & 4th clock.
Normal 2-1-1-1 burst takes 5 clocks.
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Why Burst Cycles?
• Burst Cycles more efficient at block memory
transfers (memory location is successive
locations)
– Normal cycle would take 8 clocks to transfer data from
4 locations.
– 2-1-1-1 burst takes only 5 clocks.
• Why do we want to transfer blocks of memory
efficiently?
– For cache fill operations.
– So what is a cache?
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A Cache System
Single
chip
(die)
Processor
Module
Casing
CPU
1st level
cache
Memory (SRAM)
Memory (SSRAM)
Memory (SSRAM)
Motherboard
2nd level
cache
3rd level
cache
Main Memory (DRAM)
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What is a Cache?
• The “closer” a memory is to a CPU, the faster the
data transfer between CPU and Memory.
– Can’t get any closer than on the same chip as the CPU!
• For high performance microprocessors, need
LOTS of memory
• Don’t have enough room to put all memory on
same chip as CPU
– Put some memory on same die as CPU, will not be able
to hold all needed data/programs but will hold most
frequently used data/programs
– Will need to swap out some data if we don’t find what
we need in the cache (a miss!).
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Memory Hierarchy
Access/Speed
Cost/Bit
The further
away, the
cheaper per
bit.
The further
away, the
slower the
Cache
access time,
the higher the
Main Memory capacity
(density).
Registers
Fixed Disk
Tape
Floppy
Zip
CD-ROM
CD-RWR
Capacity
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Intel 3rd
Generation
IA-64
(executes
new 64-bit
instructions)
0.13
L1 instr.
cache
IA-32 CPU
(pentium, for
compatibility)
L2 cache
cache and
memory
account for
about 70% of
the die.
L3 cache
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Main Memory and DRAM
• For main memory, we need a memory whose
primary characteristics are:
– Dense (lots o’ bits!!!)
– Cheap (cause we don’t want to spend too much for our
lots o’ bits!)
– Good at block transfers, can be rotten at random
accesses.
• How do we achieve density? (lots o’ bits?)
– Less transistors per bit!
• Dynamic RAM (DRAM) - one transistor +
capacitor per bit!!!!!
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DRAM Memory Cell
Word line
Turn this transistor
on to access data
Cs
Memory value stored
on capacitor ( a very
small capacitor...)
Bit line
Data value appears
on bit line
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DRAM Characteristics
• Very dense (high capacity). Cheap per bit.
• Slow for Random Access (access to any location)
– Cycle time >> access time, Read Cycle time = Write cycle
time.
• Has special access modes to speed block transfers
– Important since transfers to DRAM in modern computer
system is always block-oriented for cache fills.
• Only has half the address pins that you would expect
– 1M x 8 DRAM has only 10 address pins instead of 20
– Reduces package size, can pack more DRAM chips per
unit area. Address values multiplexed between
row/column addresses
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A 1M x 16 DRAM (Micron Tech.)
A0-A9 - 10 address pins
DQ1-DQ16 – 16 data pins
RAS# - row address strobe –
asserted when address pins
contain row address.
CASL#, CASH# - column
address strobe – asserted
when address pins contain
row address. Both need to be
asserted for 16 bit transfers,
only one for either high or
low byte transfers.
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Address Muxing
Assume a 16-bit data wide bus (D0-D15), and 20 address
lines A20-A1 (no A0 pin since 16 bit-wide data bus).
How are addresses split between Row, Column?
A20-A11
Row Address
CPU
A20-A1
Chip select
Decode
A10-A1
Column Address
A9-A0
DRAM
RAS#
controller
CASL#
CASH#
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Varies the
fastest.
DRAM
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DRAM Controllers
• External logic called a DRAM controller needed
to interface to DRAMs.
– DRAM interfacing more complex than SRAM
• Provides muxing of Address lines
• Assertion of RAS, CAS lines
• Also keeps DRAM contents refreshed
– Capacitors tend to leak. Memory contents needs to
continually accessed in order to keep contents valid.
– Special ‘refresh’ cycles are supported by DRAMs to
support refreshing all of bits in a row with one cycle
– DRAM controller responsible for running refresh
cycles.
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RAS asserted first
CAS asserted next
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Block transfer. Access different bits on same row, change column
address.
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Timing Values
• Random access – Trc = 104ns, Trac = 50 ns
(access time from row address strobe assertion)
• Block Mode
– Access time to data on row: 50 ns
– To column locations on same row : 25 ns
• Block transfer much more efficient than random
access.
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DRAM Chip Generations
• Each time a new DRAM Chip generation is
released, capacity goes up by 4x
– 16K x 1 (late 70’s), 64K x 1, 256K x 1, 1M x 1, 4M x
1, 16M x1, 64M x 1, 256M x 1 (current), 1G x 1
(samples available), 4G x 1 (in labs)
– Why? because of muxed addresses, 1 address pin is
actually two address bits. Two address bits give 4X
more locations.
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DRAM Modules: SIMMs and DIMMs
•
Mount Memory Device Packages on Circuit Boards to
Conserve Space
•
30-Pin SIMM – First – Single Byte Access
•
•
72-Pin SIMM – Four Byte Access
•
•
Used in “Pairs” Since in x86 1 Word=16 bits
Need Pairs for Pentium+ Since 64 bit Data Bus
168-pin DIMM – Eight Byte Access
SIMM – Single In-Line Memory Module
DIMM – Dual In-Line Memory Module
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DRAM Modules
SIMM – Single In-line Memory
Module -- 72 pins
Capacity varies
Picture shows 8M x 32 (32 MByte)
SIMMs/DIMMs invented to
get denser packaging for
DRAMs on motherboards.
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Schematic View of 72-Pin SIMM
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Memory Device Specification
•
“Dimension” of Storage Cell Array
– 8 Mb – Refers to Eight Mega-bits (not Mega-Bytes!)
8 Mb (lower case ‘b’ !!)
=(8)(1024)(1024)bits
=(1)(1024)(1024)Bytes
=1MB (upper case ‘B’!!)
Single 16Mb Device can be Arranged as:
–
–
–
–
•
16M1
4M 4
2M 8
1M 16
bits
nybbles
bytes
(words in the case of x86)
Many Devices are Typically “byte-wide” Devices
– N 8
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DRAM Variations
• SDRAM – Synchronous DRAM – has clock,
supports burst transfers
• DDR-SDRAM - Double Data Rate SDRAM
– Data transferred on EACH clock edge
– Double the data rate of SDRAM
• RDRAM – Rambus DRAM
– Will discuss this in more detail later
– High speed signaling interface to support very fast data
transfers
– Very high latency (long access time to first location),
but very fast at transferring successive locations – claim
is better at block mode transfers than SDRAM/DDRSDRAM.
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Dual Port Memories
Address
CPU
Data
Control
Address
Dual Port
Memory
(SRAM,
SSRAM)
CPU
Data
Control
Support simulatenous access via two ports (left/right sides).
Support simultaneous read accesses to different locations or same
locations.
Suports simultaneous write accesses to different locations
Simultaneous write access to same location is not supported.
One obvious application is multiple-processor systems, but useful
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in many other situations.
Flash RAM
• SRAM-like interface, density of SRAM
• Non-volatile (retains contents when power is off)
• Read Cycle time same as SRAM (10’s of
nanoseconds)
• Write Cycle >> Read Cycle
– write times in microseconds
– Can write individual locations or blocks of locations
• Applications include smart cards (credit cards,
medical history cards, etc)
• Intel is market leader, has a Flash RAM cell that
stores 2-bits per cell (can sense 4 different volage
levels from cell).
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What do you have to know?
• Differences between SRAM, DRAM in terms of
density, speed, functionality
• Pin functions of a SRAM
• Memory decoding for SRAM via PIC example
• Definitions of access time, cycle time for SRAM
• Difference between Synchronous SRAM,
Asynchronous SRAM
• Dual Port, Flash Memory definitions
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